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1.8 volt intel strataflash ? wireless memory with 3.0-volt i/o (l30) 28f640l30, 28f128l30, 28f256l30 datasheet product features the 1.8 volt intel strataflash ? wireless memory with 3-volt i/o product is the latest generation of intel strataflash ? memory devices featuring flexible, multiple-partition, dual operation. it provides high performance synchronous-burst read mode and asynchronous read mode using 1.8 volt low-voltage, multi- level cell (mlc) technology. the multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. this dual-operation architecture also allows two processors to interleave code operations while program and erase operations take place in the background. the 1.8 vo l t intel strataflash ? wireless memory with 3-volt i/o device is manufactured using intel 0.13 m etox? viii process technology. it is available in industry-standard chip scale packaging. . high performance read-while-write/erase ?85 ns initial access ?52mhz with zero wait state, 17 ns clock-to-data output synchronous-burst mode ? 25 ns asynchronous-page mode ?4-, 8-, 16-, and continuous-word burst mode ?burst suspend ? programmable wait configuration ?buffered enhanced factory programming (buffered efp): 3.5 s/byte (typ) ?1.8 v low-power buffered and non-buffered programming @ 10 s/byte (typ) architecture ? asymmetrically-blocked architecture ? multiple 8-mbit partitions: 64mb and 128mb devices ? multiple 16-mbit partitions: 256mb devices ?four 16-kword parameter blocks: top or bottom configurations ? 64k-word main blocks ? dual-operation: read-while-write (rww) or read-while-erase (rwe) ? status register for partition and device status power ?1.7 v - 2.0 v v cc operation ?i/o voltage: 2.2 v - 3.3 v ? standby current: 30 a (typ) ?4-word synchronous read current: 17 ma (typ) @ 54 mhz ? automatic power savings (aps) mode software ?20 s (typ) program suspend ?20 s (typ) erase suspend ?intel? flash data integrator (fdi) optimized ?basic command set (bcs) and extended command set (ecs) compatible ? common flash interface (cfi) capable security ?otp space: ? 64 unique device identifier bits ? 64 user-programmable otp bits ? additional 2048 user-programmable otp bits ? absolute write protection: v pp = gnd ? power-transition erase/program lockout ? individual zero-latency block locking ? individual block lock-down quality and reliability ? expanded temperature: ?25 c to +85 c ? minimum 100,000 erase cycles per block ?etox? viii process technology (0.13 m) density and packaging ?64-, 128- and 256-mbit density in vf bga packages ? 128/0, and 256/0 density in stacked-csp ? 16-bit wide data bus order number: 251903-003 april 2003 notice: this document contains information on products in the design phase of development. the information here is subject to change without notice. do not finalize a design with this information.
2 information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pat ent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. this document contains information on products in the design phase of development. the information here is subject to change without notice. do not finalize a design with this information. the 1.8 volt intel strataflash? wireless memory with 3.0 volt i/o datasheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? 2003, intel corporation * other names and brands may be claimed as the property of others.
3 28f640l30, 28f128l30, 28f256l30 contents 1.0 introduction ..................................................................................................................7 1.1 nomenclature ........................................................................................................7 1.2 acronyms ..............................................................................................................7 1.3 conventions ..........................................................................................................8 2.0 device description ....................................................................................................9 2.1 product overview ..................................................................................................9 2.2 ballout diagrams for vf bga package...............................................................10 2.3 ballout diagrams for intel? stacked chip scale package ..................................11 2.4 signal descriptions for vf bga package ...........................................................12 2.4.1 signal descriptions for 128/0 and 256/0 stacked-csp..........................13 2.5 memory map .......................................................................................................15 3.0 device operations ...................................................................................................17 3.1 bus operations....................................................................................................17 3.1.1 reads .....................................................................................................17 3.1.2 writes .....................................................................................................17 3.1.3 output disable........................................................................................17 3.1.4 standby ..................................................................................................18 3.1.5 reset ......................................................................................................18 3.2 device commands ..............................................................................................18 3.3 command definitions ..........................................................................................20 4.0 read operations .......................................................................................................22 4.1 asynchronous page-mode read ........................................................................22 4.2 synchronous burst-mode read ..........................................................................22 4.2.1 burst suspend........................................................................................23 4.3 read configuration register (rcr)....................................................................23 4.3.1 read mode.............................................................................................24 4.3.2 latency count ........................................................................................24 4.3.3 wait polarity .........................................................................................26 4.3.3.1 wait signal function................................................................26 4.3.4 data hold ...............................................................................................27 4.3.5 wait delay ............................................................................................28 4.3.6 burst sequence......................................................................................28 4.3.7 clock edge .............................................................................................28 4.3.8 burst wrap .............................................................................................28 4.3.9 burst length ...........................................................................................29 5.0 programming operations .....................................................................................30 5.1 word programming .............................................................................................30 5.1.1 factory word programming ...................................................................31 5.2 buffered programming ........................................................................................31 5.3 buffered enhanced factory programming ..........................................................32 5.3.1 buffered efp requirements and considerations ..................................32 5.3.2 buffered efp setup phase ....................................................................33 5.3.3 buffered efp program/verify phase......................................................33
28f640l30, 28f128l30, 28f256l30 4 5.3.4 buffered efp exit phase ....................................................................... 34 5.4 program suspend ............................................................................................... 34 5.5 program resume ................................................................................................ 35 5.6 program protection ............................................................................................. 35 6.0 erase operations ..................................................................................................... 36 6.1 block erase ......................................................................................................... 36 6.2 erase suspend.................................................................................................... 36 6.3 erase resume .................................................................................................... 37 6.4 erase protection.................................................................................................. 37 7.0 security modes ......................................................................................................... 38 7.1 block locking ...................................................................................................... 38 7.1.1 lock block .............................................................................................. 38 7.1.2 unlock block .......................................................................................... 38 7.1.3 lock-down block ................................................................................... 38 7.1.4 block lock status................................................................................... 39 7.1.5 block locking during suspend .............................................................. 39 7.2 protection registers ............................................................................................ 40 7.2.1 reading the protection registers .......................................................... 41 7.2.2 programming the protection registers .................................................. 42 7.2.3 locking the protection registers ........................................................... 42 8.0 dual-operation considerations ......................................................................... 43 8.1 memory partitioning ............................................................................................ 43 8.2 read-while-write command sequences ........................................................... 43 8.2.1 simultaneous operation details............................................................. 44 8.2.2 synchronous and asynchronous read-while-write characteristics and waveforms ............................................................. 44 8.2.2.1 write operation to asynchronous read transition....................... 44 8.2.2.2 synchronous read to write operation transition ......................... 45 8.2.3 read operation during buffered programming flowchart..................... 45 8.3 simultaneous operation restrictions .................................................................. 46 9.0 special read states ................................................................................................ 47 9.1 read status register .......................................................................................... 47 9.1.1 clear status register ............................................................................. 48 9.2 read device identifier ......................................................................................... 48 9.3 cfi query............................................................................................................ 49 10.0 power and reset ...................................................................................................... 50 10.1 power-up/down characteristics ......................................................................... 50 10.2 power supply decoupling ................................................................................... 50 10.3 automatic power saving (aps) .......................................................................... 50 10.4 reset characteristics .......................................................................................... 50 11.0 thermal and dc characteristics ........................................................................ 52 11.1 absolute maximum ratings ................................................................................ 52 11.2 operating conditions .......................................................................................... 52 11.3 dc current characteristics ................................................................................. 53 11.4 dc voltage characteristics ................................................................................. 54
5 28f640l30, 28f128l30, 28f256l30 12.0 ac characteristics ...................................................................................................55 12.1 ac read specifications (vccq = 2.2 v ? 3.3 v) ................................................55 12.2 ac write specifications.......................................................................................60 12.3 program and erase characteristics ....................................................................64 12.4 reset specifications............................................................................................64 12.5 ac test conditions .............................................................................................65 12.6 capacitance ........................................................................................................66 appendix a write state machine (wsm) ...........................................................................67 appendix b flowcharts ............................................................................................................74 appendix c common flash interface ................................................................................83 appendix d mechanical information ...................................................................................93 appendix e additional information .....................................................................................97 appendix f ordering information for vf bga package ............................................98 appendix g ordering information for s-csp package ...............................................99
28f640l30, 28f128l30, 28f256l30 6 revision history revision date revision description 10/14/02 -001 initial release 02/08/03 -002 revised 256mb partition size revised 256mb memory map changed wait function to de-assert during asynchronous operations (asyn- chronous reads and all writes) changed wait function to active during synchronous non-array read updated all waveforms to reflect new wait function revised section 8.2.2 added synchronous read to write transition section added new ac specs: r15, r16, r17, r111, r311, r312, w21, and w22 various text edits 04/11/03 -003 improved bin 1 to 85ns from 90ns improved frequency to 52mhz from 50mhz added stacked-csp for 128/0 and 256/0 ball-out and mechanical drawing
28f640l30, 28f128l30, 28f256l30 datasheet 7 1.0 introduction this document provides information about the 1.8 volt intel strataflash ? wireless memory with 3-volt i/o (l30) device. this document describes the l30 flash memory device features, operation, and specifications. 1.1 nomenclature 1.8 v : v cc voltage range of 1.7 v ? 2.0 v (except where noted) 3.0 v range : v ccq voltage range of 2.2 v ? 3.3 v vpp = 9.0 v : v pp voltage range of 8.5 v ? 9.5 v block : a group of bits, bytes or words within the flash memory array that erase simultaneously when the erase command is issued to the device. the l30 flash memory device has two block sizes: 16k-word, and 64k-word. main block : an array block that is usually used to store code and/or data. main blocks are larger than parameter blocks. parameter block : an array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in eeprom. to p parameter device : previously referred to as a top-boot device, a device with its parameter partition located at the highest physical address of its memory map. parameter blocks within a parameter partition are located at the highest physical address of the parameter partition. bottom parameter device : previously referred to as a bottom-boot device, a device with its parameter partition located at the lowest physical address of its memory map. parameter blocks within a parameter partition are located at the lowest physical address of the parameter partition. partition : a group of blocks that share common program/erase circuitry. blocks within a partition also share a common status register. if any block within a partition is being programmed or erased, only status register data (rather than array data) is available when any address within that partition is read. main partition : a partition containing only main blocks. parameter partition : a partition containing parameter blocks and main blocks. 1.2 acronyms cui: command user interface mlc : multi-level cell otp : one-time programmable plr : protection lock register pr : protection register rcr : read configuration register rfu : reserved for future use sr : status register wsm : write state machine
28f640l30, 28f128l30, 28f256l30 8 datasheet 1.3 conventions vcc: signal or voltage connection v cc : signal or voltage level 0x : hexadecimal number prefix 0b : binary number prefix sr[4] : denotes an individual register bit. a[15:0]: denotes a group of similarly named signals, such as address or data bus. a5 : denotes one element of a signal group membership, such as an address. bit: binary unit byte: eight bits word: two bytes, or sixteen bits kbit: 1024 bits kbyte: 1024 bytes kword: 1024 words mbit: 1,048,576 bits mbyte: 1,048,576 bytes mword: 1,048,576 words
28f640l30, 28f128l30, 28f256l30 datasheet 9 2.0 device description this section provides an overview of the features and capabilities of the 1.8 volt intel strataflash ? wireless memory with 3-volt i/o (l30) device. 2.1 product overview the 1.8 volt intel strataflash ? wireless memory with 3-volt i/o (l30) device provides read-while- write and read-while-erase capability with density upgrades through 256-mbit. this family of devices provides high performance at low voltage on a 16-bit data bus. individually erasable memory blocks are sized for optimum code and data storage. each device density contains one parameter partition and several main partitions. the flash memory array is grouped into multiple 8-mbit partitions. by dividing the flash memory into partitions, program or erase operations can take place at the same time as read operations. although each partition has write, erase and burst read capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in read mode. the l30 flash memory device allows burst reads that cross partition boundaries. user application code is responsible for ensuring that burst reads don?t cross into a partition that is programming or erasing. upon initial power up or return from reset, the device defaults to asynchronous page-mode read. configuring the read configuration register enables synchronous burst-mode reads. in synchronous burst mode, output data is synchronized with a user-supplied clock signal. a wa it signal provides easy cpu-to-flash memory synchronization. in addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. designed for low-voltage systems, the l30 flash memory device supports read operations with v cc at 1.8 v, and erase and program operations with v pp at 1.8 v or 9.0 v. buffered enhanced factory programming (buffered efp) provides the fastest flash array programming performance with v pp at 9.0 volt, which increases factory throughput. with v pp at 1.8 v, vcc and vpp can be tied together for a simple, ultra low power design. in addition to voltage flexibility, a dedicated v pp connection provides complete data protection when v pp is less than v pplk . a command user interface (cui) is the interface between the system processor and all internal operations of the device. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase and program. a status register indicates erase or program completion and any errors that may have occurred. an industry-standard command sequence invokes program and erase automation. each erase operation erases one block. the erase suspend feature allows system software to pause an erase cycle to read or program data in another block. program suspend allows system software to pause programming to read other locations. data is programmed in word increments (x16). the l30 flash memory device offers power savings through automatic power savings (aps) mode and standby mode. the device automatically enters aps following read-cycle completion. standby is initiated when the system deselects the device by deasserting ce# or by asserting rst#. combined, these features can significantly reduce power consumption. the l30 flash memory device?s protection register allows unique flash device identification that can be used to increase system security. also, the individual block lock feature provides zero- latency block locking and unlocking.
28f640l30, 28f128l30, 28f256l30 10 datasheet 2.2 ballout diagrams for vf bga package the l30 flash memory device is available in a vf bga package with 0.75 mm ball-pitch. figure 1 shows the ballout for the 64-mbit and 128-mbit devices in the 56-ball vf bga package with a 7 x 8 active-ball matrix. figure 2 shows the device ballout for the 256-mbit device in the 63-ball vf bga package with a 7 x 9 active-ball matrix. both package densities are ideal for space- constrained board applications note: on lower-density devices, upper-address balls can be treated as nc. (e.g., for 64-mbit density, a22 will be nc) note: on lower density devices upper address balls can be treated as rfus. (a24 is for 512mb and a25 is for 1gb densities.) all ball locations are populated. figure 1.7x8 active-ball matrix for 64-, and 128-mbit densities in vf bga packages figure 2.7x9 active-ball matrix for 256-mbit density in vf bga package vfbga 7x8 bottom view - bal l side up vfbga 7x8 top view - ball side down 2345678 1 a8 vss vcc vpp a18 a6 a4 a9 a20 clk rst# a17 a5 a3 a10 a21 w e# a19 a7 a2 a14 wait a16 d12 wp# a22 d15 d6 d4 d2 d1 ce# a0 d14 d13 d11 d10 d9 d0 oe# adv# a1 vssq vcc d3 vccq d8 vssq a11 a12 a13 a15 vccq vss d7 d5 a b c d e f g 2 3 4 5 6 7 81 a8 vss vcc vpp a18 a6 a4 a9 a20 clk rst# a17 a5 a3 a10 a21 we# a19 a7 a2 a14 wait a16 d12 wp# a22 d15 d6 d4 d2 d1 ce# a0 d14 d13 d11 d10 d9 d0 oe# adv# a1 vssq vcc d3 vccq d8 vssq a11 a12 a13 a15 vccq vss d7 d5 a b c d e f g rfu vcc a4 a6 a18 vpp vss a8 a11 rfu clk a3 a5 a17 rst# a20 a9 a12 a25 adv# a2 a7 a19 we# a21 a10 a13 a24 a16 a1 a22 wp# d12 wait a14 a15 a23 d4 a0 ce# d1 d2 d6 d15 vccq rfu d11 oe# d0 d9 d10 d13 d14 vs s rfu vcc vssq d8 vccq d3 d5 vssq d7 bottom view - ball side up a b c d e f g du du du du du du du du du du du du du du du du 11 10 12 13 7 5 4 3 2 1 8 96 rfu vcc a4 a6 a18 vpp vss a8 a11 rfu clk a3 a5 a17 rst# a20 a9 a12 a25 adv# a2 a7 a19 we # a21 a10 a13 a24 a16 a1 a22 wp # d12 wai t a14 a15 a23 d4 a0 ce# d1 d2 d6 d15 vccq rfu d11 oe# d0 d9 d10 d13 d14 vss rfu vcc vssq d8 vccq d3 d5 vssq d7 top view - ball side down a b c d e f g du du du du du du du du du du du du du du du du 11 10 12 13 7 5 4 3 2 1 89 6
28f640l30, 28f128l30, 28f256l30 datasheet 11 2.3 ballout diagrams for intel ? stacked chip scale package the 1.8 volt intel strataflash ? wireless memory in quad+ ballout device is available in an 88-ball (80-active ball) intel ? stacked chip scale package for the 128-mbit device and in an 88-ball (80- active ball) intel ? ultra-thin stacked chip scale package for the 256-mbit device. figure 3 shows the signal ballout. refer to section 5.0 for mechanical package information. figure 3.88-ball (80-active ball) stacked-csp package ballout flash sp e cific sram /psram specific global legend: top view - b a ll side down 8 7 6 5 4 3 2 1 a b c d e f g h j k l m du a4 du du du du du du du a5 a3 a2 a7 a1 a6 a0 a18 a19 vss vss a23 a24 a25 a17 f2-vcc clk a21 a22 a12 a11 a13 a9 p1-cs# f-vpp, f-vpen a20 a10 a15 f-we # a8 d8 d2 d10 d5 d13 wait a14 a16 f1-ce# p-mode vss vss vss p2-cs# f1-vcc f2-vcc vccq f3 -ce# d0 d1 d9 d3 d4 d6 d7 d15 d11 d12 d14 f1-o e # f2-o e# p-vcc s-cs2 r-we# r-ub# r-lb# r-oe# s-vcc s-cs1# f1 -v cc f-w p# adv# f-rst# f2-ce# vccq vss vss vccq vss
28f640l30, 28f128l30, 28f256l30 12 datasheet 2.4 signal descriptions for vf bga package table 1 describes the active signals used on the l30 flash memory device. table 1. signal descriptions symbol type name and function a[max:0] in address: device address inputs. 64-mbit: a[21:0]; 128-mbit: a[22:0]; 256-mbit: a[23:0]. d[15:0] in/out data input/outputs: inputs data and commands during write cycles; outputs data during memory, status register, protection register, and read configuration register reads. data balls float when the ce# or oe# are de-asserted. data is internally latched during writes. adv# in address valid: active-low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous mode, the address is latched when adv# going high or continuously flows through if adv# is held low. ce# in chip enable: active-low input. ce#-low selects the device. ce#-high deselects the device, placing it in standby, with d[15:0] and wait in high-z. clk in clock: synchronizes the device with the system?s bus frequency in synchronous-read mode and increments the internal address generator. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. oe# in output enable: active-low input. oe#-low enables the device?s output data buffers during read cycles. oe#-high places the data outputs in high-z and wait in high-z. rst# in reset: active-low input. rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. rst#-high enables normal operation. exit from reset places the device in asynchronous read array mode. wait out wait: indicates data valid in synchronous array or non-array burst reads. configuration register bit 10 (cr.10, wt) determines its polarity when asserted. with ce# and oe# at v il , wait?s active output is v ol or v oh when ce# and oe# are asserted. wait is high-z if ce# or oe# is v ih . ?in synchronous array or non-array read modes, wait indicates invalid data when asserted and valid data when de-asserted. ?in asynchronous page mode, and all write modes, wait is de-asserted. we# in write enable: active-low input. we# controls writes to the device. address and data are latched on the rising edge of we#. wp# in write protect: active-low input. wp#-low enables the lock-down mechanism. blocks in lock-down cannot be unlocked with the unlock command. wp#-high overrides the lock-down function enabling blocks to be erased or programmed using software commands. vpp pwr/l erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v cc for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v pp1 min. v pp must remain above v pp1 min to perform in-system flash modification. vpp may be 0 v during read operations. v pp2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. vpp can be connected to 12 v for a cumulative total not to exceed 80 hours. extended use of this pin at 12 v may reduce block cycling capability. vcc pwr device core power supply: core (logic) source voltage. writes to the flash array are inhibited when v cc v lko . operations at invalid v cc voltages should not be attempted. vccq pwr output power supply: output-driver source voltage. vss pwr ground: ground reference for device logic voltages. connect to system ground. vssq pwr ground: ground reference for device output voltages. connect to system ground. du - don?t use: do not use this ball. this ball should not be connected to any power supplies, signals or other balls, and must be left floating. nc - no connect: no internal connection; can be driven or floated. rfu - reserved for future use: reserved by intel for future device functionality and enhancement.
28f640l30, 28f128l30, 28f256l30 datasheet 13 2.4.1 signal descriptions for 128/0 and 256/0 stacked-csp table 2 describes the active signals used on the 128/0 and 256/0-mbit s-csp. table 2. device signal descriptions for s-csp (sheet 1 of 2) symbol type description a[max:0] input address inputs: inputs for all die addresses during read and write operations. ? 128-mbit die: a[max] = a22 ? 256-mbit die: a[max] = a23 d[15:0] input/ output data inputs/outputs: inputs data and commands during write cycles, outputs data during read cycles. data signals float when the device or its outputs are deselected. data is internally latched during writes. ce#1 ce#2 input flash chip enable: low-true: ce#-low selects the associated flash memory die. when asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the associated flash die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z state. ce#1 selects flash die #1; ce#2 selects flash die #2. ce#2 is available on stacked combinations with two flash die and is rfu (reserved for future use) on stacked combinations with only one flash die. s-cs1# s-cs2 input sram chip selects: when both sram chip selects are asserted, sram internal control logic, input buffers, decoders, and sense amplifiers are active. when either/ both sram chip selects are deasserted (s-cs1# = vih or s-cs2 = vil), the sram is deselected and its power is reduced to standby levels. treat this signal as nc (no connect) for this device. p-cs# input psram chip select: low-true; when asserted, psram internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the psram is deselected and its power is reduced to standby levels. treat this signal as nc (no connect) for this device. oe#1 oe#2 input flash output enable: low-true; oe#-low enables the flash output buffers. oe#-high disables the flash output buffers, and places the flash outputs in high-z. oe#1 controls the outputs of flash die #1; oe#2 controls the outputs of flash die #2. oe#2 is available on stacked combinations with two flash die and is rfu on stacked combinations with only one flash die. r-oe# input ram output enable: low-true; r-oe#-low enables the selected ram output buffers. r-oe#-high disables the ram output buffers, and places the selected ram outputs in high-z. treat this signal as nc (no connect) for this device. we# input flash write enable: low-true; we# controls writes to the selected flash die. address and data are latched on the rising edge of we#. r-we# input ram write enable: low-true; r-we# controls writes to the selected ram die. treat this signal as nc (no connect) for this device. clk input flash clock: synchronizes the device with the system?s bus frequency in synchronous-read mode and increments the internal address generator. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. wait output flash wait: indicates data valid in synchronous array or non-array burst reads. configuration register bit 10 (cr.10, wt) determines its polarity when asserted. with ce# and oe# at v il , wait?s active output is v ol or v oh when ce# and oe# are asserted. wait is high-z if ce# or oe# is v ih . ?in synchronous array or non-array read modes, wait indicates invalid data when asserted and valid data when de-asserted. ?in asynchronous page mode, and all write modes, wait is de-asserted.
28f640l30, 28f128l30, 28f256l30 14 datasheet wp# input flash write protect: low-true; wp# enables/disables the lock-down protection mechanism of the selected flash die. wp#-low enables the lock-down mechanism - locked down blocks cannot be unlocked with software commands. wp#-high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. adv# input flash address va lid : active-low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous mode, the address is latched when adv# going high or continuously flows through if adv# is held low. r-ub# r-lb# input ram upper / lower byte enables: low-true; during ram reads, r-ub#-low enables the ram high order bytes on d[15:8], and r-lb#-low enables the ram low- order bytes on d[7:0]. treat this signal as nc (no connect) for this device. rst# input flash reset: low-true; rst#-low initializes flash internal circuitry and disables flash operations. rst#-high enables flash operation. exit from reset places the flash in asynchronous read array mode. p-mode input psram mode: low-true; p-mode is used to program the configuration register, and enter/exit low power mode. treat this signal as nc (no connect) for this device. vpp, vpen power flash program / erase power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v cc for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v pp1 min. v pp must remain above v pp1 min to perform in-system flash modification. vpp may be 0 v during read operations. v pp2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. vpp can be connected to 12 v for a cumulative total not to exceed 80 hours. extended use of this pin at 12 v may reduce block cycling capability vpen ((erase/program/block lock enables) is not available for l18/l30 products. vcc1 vcc2 power flash logic power: vcc1 supplies power to the core logic of flash die #1; vcc2 supplies power to the core logic of flash die #2. write operations are inhibited when v cc < v lko . device operations at invalid v cc voltages should not be attempted. s-vcc power sram power supply: supplies power for sram operations. treat this signal as nc (no connect) for this device. p-vcc power psram power supply: supplies power for psram operations. treat this signal as nc (no connect) for this device. vccq power flash i/o power: supply power for the input and output buffers. vss power ground: connect to system ground. do not float any vss connection. rfu reserved for future use: reserve for future device functionality/ enhancements. contact intel regarding their future use. du don?t use: do not connect to any other signal, or power supply; must be left floating. nc no connect: no internal connection; can be driven or floated. table 2. device signal descriptions for s-csp (sheet 2 of 2)
28f640l30, 28f128l30, 28f256l30 datasheet 15 2.5 memory map the 64mb and 128mb memory array is divided into multiple 8-mbit partitions. each device density contains one parameter partition and several main partitions. the 8-mbit top or bottom parameter partition contains four 16k-word blocks and seven 64k-word blocks. there are multiple 8-mbit main partitions. the 8-mbit main partitions each contains eight 64k-word blocks. the device multi-partition architecture is divided as follow: ? the 64-mbit device contains eight partitions: one 8-mbit parameter partition, seven 8-mbit main partitions. ? the 128-mbit device contains sixteen partitions: one 8-mbit parameter partition, fifteen 8- mbit main partitions. ? the 256mb memory array is divided into multiple 16-mbit partitions. each device contains one parameter partition and fifteen main partitions. the 16-mbit top or bottom parameter partition contains four 16k-word blocks and fifteen 64k-word blocks. there are fifteen 16- mbit main partitions. the 16-mbit main partitions each contains sixteen 64k-word blocks. table 3 and table 4 show the top and bottom parameter memory maps. table 3. top parameter memory map size (kw) blk 64-mbit size (kw) blk 128-mbit 43 8-mbit parameter partition one partition 16 66 3fc000-3fffff 8-mbit parameter partition one partition 16 130 7fc000-7fffff 16 65 3f8000-3fbfff 16 129 7f8000-7fbfff 16 64 3f4000-3f7fff 16 128 7f4000-7f7fff 16 63 3f0000-3f3fff 16 127 7f0000-7f3fff 64 62 3e0000-3effff 64 126 7e0000-7effff ? ? ? ? ? ? 64 56 380000-38ffff 64 120 780000-78ffff 8-mbit main partition seven partitions 64 55 370000-37ffff 8-mbit main partitions fifteen partitions 64 119 770000-77ffff ? ? ? ? 64 0 000000-00ffff 64 0 000000-00ffff size (kw) blk 256-mbit 16-mbit parameter partition one partition 16 258 ffc000-ffffff 16 257 ff8000-ffbfff 16 256 ff4000-ff7fff 16 255 ff0000-ff3fff 64 254 fe0000-feffff ? ? ? 64 240 f00000-ffffff 16-mbit main partitions seven partitions 64 239 ef0000-efffff ? 64 128 800000-80ffff eight partitions 64 127 7f0000-7fffff ? 64 0 000000-00ffff
28f640l30, 28f128l30, 28f256l30 16 datasheet table 4. bottom parameter memory map size (kw) blk 64-mbit size (kw) blk 128-mbit 8-mbit main partitions seven partitions 64 66 3f0000-3fffff 8-mbit main partitions fifteen partitions 64 130 7f0000-7fffff ? ? ? ? ? ? 64 11 080000-08ffff 64 11 080000-08ffff 8-mbit parameter partition one partition 64 10 070000-07ffff 8-mbit parameter partition one partition 64 10 070000-07ffff ? ? ? ? ? ? 64 4 010000-01ffff 64 4 010000-01ffff 16 3 00c000-00ffff 16 3 00c000-00ffff 16 2 008000-00bfff 16 2 008000-00bfff 16 1 004000-007fff 16 1 004000-007fff 16 0 000000-003fff 16 0 000000-003fff size (kw) blk 256-mbit 16-mbit main partitions eight partitions 64 258 ff0000-ffffff ? ? ? 64 131 100000-10ffff seven partitions 64 130 7f0000-7fffff ? ? ? 64 19 100000-10ffff 16-mbit parameter partition one partition 64 18 0f0000-0fffff ? ? ? 64 4 010000-01ffff 16 3 00c000-00ffff 16 2 008000-00bfff 16 1 004000-007fff 16 0 000000-003fff
28f640l30, 28f128l30, 28f256l30 datasheet 17 3.0 device operations this section provides an overview of device operations. the system cpu provides control of all in- system read, write, and erase operations of the device via the system bus. the on-chip write state machine (wsm) manages all block-erase and word-program algorithms. device commands are written to the command user interface (cui) to control all flash memory device operations. the cui does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. 3.1 bus operations ce#-low and rst# high enable device read operations. the device internally decodes upper address inputs to determine the accessed partition. adv#-low opens the internal address latches. oe#-low activates the outputs and gates selected data onto the i/o bus. in asynchronous mode, the address is latched when adv# goes high or continuously flows through if adv# is held low. in synchronous mode, the address is latched by the first of either the rising adv# edge or the next valid clk edge with adv# low (we# and rst# must be vih; ce# must be vil). 3.1.1 reads to perform a read operation, rst# and we# must be deasserted while ce# and oe# are asserted. ce# is the device-select control. when asserted, it enables the flash memory device. oe# is the data-output control. when asserted, the addressed flash memory data is driven onto the i/o bus. see section 4.0, ?read operations? on page 22 for details on the available read modes, and see section 9.0, ?special read states? on page 47 for details regarding the available read states. the automatic power savings (aps) feature provides low power operation following reads during active mode. after data is read from the memory array and the address lines are quiescent, aps automatically places the device into standby. in aps, device current is reduced to i ccaps (see section 11.3, ?dc current characteristics? on page 53 ). 3.1.2 writes to perform a write operation, both ce# and we# are asserted while rst# and oe# are deasserted. during a write operation, address and data are latched on the rising edge of we# or ce#, whichever occurs first. table 5, ?command bus cycles? on page 19 shows the bus cycle sequence for each of the supported device commands, while table 6, ?command codes and definitions? on page 20 describes each command. see section 12.0, ?ac characteristics? on page 55 for signal- timing details. note: write operations with invalid v cc and/or v pp voltages can produce spurious results and should not be attempted. 3.1.3 output disable when oe# is deasserted, device outputs d[15:0] are disabled and placed in a high - impedance (high-z) state, wai t is also placed in high-z.
28f640l30, 28f128l30, 28f256l30 18 datasheet 3.1.4 standby when ce# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. in standby, the data outputs are placed in high-z, independent of the level placed on oe#. standby current, i ccs , is the average current measured over any 5 ms time interval, 5 s after ce# is deasserted. during standby, average current is measured over the same time interval 5 s after ce# is deasserted. when the device is deselected (while ce# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 3.1.5 reset as with any automated device, it is important to assert rst# when the system is reset. when the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. if a cpu reset occurs with no flash memory reset, improper cpu initialization may occur because the flash memory may be providing status information rather than array data. intel ? flash memory devices allow proper cpu initialization following a system reset through the use of the rst# input. rst# should be controlled by the same low-true reset signal that resets the system cpu. after initial power-up or reset, the device defaults to asynchronous read array, and the status register is set to 0x80. asserting rst# de-energizes all internal circuits, and places the output drivers in high-z. when rst# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. when rst# has been deasserted, the device is reset to asynchronous read array state. note: if rst# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. when returning from a reset (rst# deasserted), a minimum wait is required before the initial read access outputs valid data. also, a minimum delay is required after a reset before a write cycle can be initiated. after this wake - up interval passes, normal operation is restored. see section 12.0, ?ac characteristics? on page 55 for details about signal-timing. 3.2 device commands device operations are initiated by writing specific device commands to the command user interface (cui). see table 5, ?command bus cycles? on page 19 . several commands are used to modify array data including wo rd program and block erase commands. writing either command to the cui initiates a sequence of internally - timed functions that culminate in the completion of the requested task. however, the operation can be aborted by either asserting rst# or by issuing an appropriate suspend command.
28f640l30, 28f128l30, 28f256l30 datasheet 19 table 5. command bus cycles mode command bus cycles first bus cycle second bus cycle oper addr 1 data 2 oper addr 1 data 2 read read array 1 write pna 0xff read device identifier 2 write pna 0x90 read pba+ia id cfi query 2 write pna 0x98 read pna+qa qd read status register 2 write pna 0x70 read pna srd clear status register 1 write x 0x50 program word program 2 write wa 0x40/ 0x10 write wa wd buffered program 3 2writewa0xe8writewa n - 1 buffered enhanced factory program (buffered efp) 4 > 2 write wa 0x80 write wa 0xd0 erase block erase 2 write ba 0x20 write ba 0xd0 suspend program/erase suspend 1 write x 0xb0 program/erase resume 1 write x 0xd0 block locking/ unlocking lock block 2 write ba 0x60 write ba 0x01 unlock block 2 write ba 0x60 write ba 0xd0 lock-down block 2 write ba 0x60 write ba 0x2f protection program protection register 2 write pra 0xc0 write pra pd program lock register 2 write lra 0xc0 write lra lrd configuration program read configuration register 2 write rcd 0x60 write rcd 0x03 notes: 1. first command cycle address should be the same as the operation?s target address. pna = address within the partition. pba = partition base address. ia = identification code address offset. qa = cfi query address offset. ba = address within the block. wa = word address of memory location to be written. pra = protection register address. lra = lock register address. x = any valid address within the device. 2. id = identifier data. qd = query data on d[15:0]. srd = status register data. wd = word data. n = word count of data to be loaded into the write buffer. pd = protection register data. pd = protection register data. lrd = lock register data. rcd = read configuration register data on a[15:0]. a[max:16] can select any partition . 3. the second cycle of the buffered program command is the word count of the data to be loaded into the write buffer. this is followed by up to 32 words of data.then the confirm command (0xd0) is issued, triggering the array programming operation. 4. the confirm command (0xd0) is followed by the buffer data.
28f640l30, 28f128l30, 28f256l30 20 datasheet 3.3 command definitions va l i d device command codes and descriptions are shown in table 6 . table 6. command codes and definitions (sheet 1 of 2) mode code device mode description read 0xff read array places the addressed partition in read array mode. array data is output on d[15:0]. 0x70 read status register places the addressed partition in read status register mode. the partition enters this mode after a program or erase command is issued. status register data is output on d[7:0]. 0x90 read device id or configuration register places the addressed partition in read device identifier mode. subsequent reads from addresses within the partition outputs manufacturer/device codes, configuration register data, block lock status, or protection register data on d[15:0]. 0x98 read query places the addressed partition in read query mode. subsequent reads from the partition addresses output common flash interface information on d[7:0]. 0x50 clear status register the wsm can only set status register error bits. the clear status register command is used to clear the sr error bits. write 0x40 word program setup first cycle of a 2-cycle programming command; prepares the cui for a write operation. on the next write cycle, the address and data are latched and the wsm executes the programming algorithm at the addressed location. during program operations, the partition responds only to read status register and program suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the status register data for synchronous non-array read. the read array command must be issued to read array data after programming has finished. 0x10 alternate word program setup equivalent to the word program setup command, 0x40. 0xe8 buffered program this command loads a variable number of bytes up to the buffer size of 32 words onto the program buffer. 0xd0 buffered program confirm the confirm command is issued after the data streaming for writing into the buffer is done. this instructs the wsm to perform the buffered program algorithm, writing the data from the buffer to the flash memory array. 0x80 buffered enhanced factory programming setup first cycle of a 2-cycle command; initiates buffered enhanced factory program mode (buffered efp). the cui then waits for the buffered efp confirm command, 0xd0, that initiates the buffered efp algorithm. all other commands are ignored when buffered efp mode begins. 0xd0 buffered efp confirm if the previous command was buffered efp setup (0x80), the cui latches the address and data, and prepares the device for buffered efp mode. erase 0x20 block erase setup first cycle of a 2-cycle command; prepares the cui for a block-erase operation. the wsm performs the erase algorithm on the block addressed by the erase confirm command. if the next command is not the erase confirm (0xd0) command, the cui sets status register bits sr[4] and sr[5], and places the addressed partition in read status register mode. 0xd0 block erase confirm if the first command was block erase setup (0x20), the cui latches the address and data, and the wsm erases the addressed block. during block-erase operations, the partition responds only to read status register and erase suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the status register data for synchronous non-array read. suspend 0xb0 program or erase suspend this command issued to any device address initiates a suspend of the currently-executing program or block erase operation. the status register indicates successful suspend operation by setting either sr[2] (program suspended) or sr[6] (erase suspended), along with sr[7] (ready). the write state machine remains in the suspend mode regardless of control signal states (except for rst# asserted). 0xd0 suspend resume this command issued to any device address resumes the suspended program or block-erase operation.
28f640l30, 28f128l30, 28f256l30 datasheet 21 block locking/ unlocking 0x60 lock block setup first cycle of a 2-cycle command; prepares the cui for block lock configuration changes. if the next command is not block lock (0x01), block unlock (0xd0), or block lock-down (0x2f), the cui sets status register bits sr[4] and sr[5], indicating a command sequence error. 0x01 lock block if the previous command was block lock setup (0x60), the addressed block is locked. 0xd0 unlock block if the previous command was block lock setup (0x60), the addressed block is unlocked. if the addressed block is in a lock-down state, the operation has no effect. 0x2f lock-down block if the previous command was block lock setup (0x60), the addressed block is locked down. protection 0xc0 program protection register setup first cycle of a 2-cycle command; prepares the device for a protection register or lock register program operation. the second cycle latches the register address and data, and starts the programming algorithm configu- ration 0x60 read configuration register setup first cycle of a 2-cycle command; prepares the cui for device read configuration. if the set read configuration register command (0x03) is not the next command, the cui sets status register bits sr[4] and sr[5], indicating a command sequence error. 0x03 read configuration register if the previous command was read configuration register setup (0x60), the cui latches the address and writes a[15:0] to the read configuration register. following a configure read configuration register command, subsequent read operations access array data. table 6. command codes and definitions (sheet 2 of 2) mode code device mode description
28f640l30, 28f128l30, 28f256l30 22 datasheet 4.0 read operations the device supports two read modes: asynchronous page mode and synchronous burst mode. asynchronous page mode is the default read mode after device power-up or a reset. the read configuration register must be configured to enable synchronous burst reads of the flash memory array (see section 4.3, ?read configuration register (rcr)? on page 23 ). each partition of the device can be in any of four read states: read array, read identifier, read status or read query. upon power-up, or after a reset, all partitions of the device default to read array. to change a partition?s read state, the appropriate read command must be written to the device (see section 3.2, ?device commands? on page 18 ). see section 9.0, ?special read states? on page 47 for details regarding read status, read id, and cfi query modes. the following sections describe read-mode operations in detail. 4.1 asynchronous page-mode read following a device power-up or reset, asynchronous page mode is the default read mode and all partitions are set to read array. however, to perform array reads after any other device operation (e.g. write operation), the read array command must be issued in order to read from the flash memory array. note: asynchronous page-mode reads can only be performed when read configuration register bit rcr[15] is set (see section 4.3, ?read configuration register (rcr)? on page 23 ). to perform an asynchronous page-mode read, an address is driven onto a[max:0], and ce# and adv# are asserted. we# and rst# must already have been deasserted. wai t is de-asserted during asynchronous page mode. adv# can be driven high to latch the address, or it must be held low throughout the read cycle. clk is not used for asynchronous page-mode reads, and is ignored. if only asynchronous reads are to be performed, clk should be tied to a valid v ih level, wa i t signal can be floated and adv# must be tied to ground. array data is driven onto d[15:0] after an initial access time t avqv delay. (see section 12.0, ?ac characteristics? on page 55 ). in asynchronous page mode, four data words are ?sensed? simultaneously from the flash memory array and loaded into an internal page buffer. the buffer word corresponding to the initial address on a[max:0] is driven onto d[15:0] after the initial access delay. address bits a[max:2] select the 4-word page. address bits a[1:0] determine which word of the 4-word page is output from the data buffer at any given time. 4.2 synchronous burst-mode read read configuration register bits cr[15:0] must be set before synchronous burst operation can be performed. synchronous burst mode can be performed for both array and non-array reads such as read id, read status or read query. (see section 4.3, ?read configuration register (rcr)? on page 23 for details). synchronous burst mode outputs 4-, 8-, 16-, or continuous-words. to perform a synchronous burst- read, an initial address is driven onto a[max:0], and ce# and adv# are asserted. we# and rst# must already have been deasserted. adv# is asserted, and then deasserted to latch the address. alternately, adv# can remain asserted throughout the burst access, in which case the address is latched on the next valid clk edge while adv# is asserted.
28f640l30, 28f128l30, 28f256l30 datasheet 23 during synchronous array and non-array read modes, the first word is output from the data buffer on the next valid clk edge after the initial access latency delay (see section 4.3.2, ?latency count? on page 24 ). subsequent data is output on valid clk edges following a minimum delay. however, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. during synchronous read operations, wai t is driven with respect to oe# assertion. wa i t indicates invalid data when asserted, and valid data when de-asserted with respect to a valid clock edge. see figure 16 through figure 18 for additional details. 4.2.1 burst suspend the burst suspend feature of the device can reduce or eliminate the initial access latency incurred when system software needs to suspend a burst sequence that is in progress in order to retrieve data from another device on the same system bus. the system processor can resume the burst sequence later. burst suspend provides maximum benefit in non-cache systems. burst accesses can be suspended during the initial access latency (before data is received) or after the device has output data. when a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. a burst sequence can be suspended and resumed without limit as long as device operation conditions are met. burst suspend occurs when ce# is asserted, the current address has been latched (either adv# rising edge or valid clk edge), clk is halted, and oe# is deasserted. clk can be halted when it is at v ih or v il . wai t is in high-z during oe# de-assertion. to resume the burst access, oe# is reasserted, and clk is restarted. subsequent clk edges resume the burst sequence. within the device, ce# and oe# gate wai t. therefore, during burst suspend wai t is placed in high-impedance state when oe# is de-asserted and resumed active when oe# is re-asserted. see figure 19, ?burst suspend timing? on page 59 . 4.3 read configuration register (rcr) the rcr is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. to modify rcr settings, use the configure read configuration register command (see section 3.2, ?device commands? on page 18 ). rcr contents can be examined using the read device identifier command, and then reading from + 0x05 (see section 9.2, ?read device identifier? on page 48 ). the rcr is shown in table 7 . the following sections describe each rcr bit. table 7. read configuration register description (sheet 1 of 2) read configuration register (rcr) read mode res latency count wait polarity data hold wait delay burst seq clk edge res res burst wrap burst length rm r lc[2:0] wp dh wd bs ce r r bw bl[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name description
28f640l30, 28f128l30, 28f256l30 24 datasheet 4.3.1 read mode the read mode (rm) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. when the rm bit is set, asynchronous page mode is selected (default). when rm is cleared, synchronous burst mode is selected. 4.3.2 latency count the latency count bits, lc[2:0], tell the device how many clock cycles must elapse from the rising edge of adv# (or from the first valid clock edge after adv# is asserted) until the first data word is to be driven onto d[15:0]. the input clock frequency is used to determine this value. figure 4 shows the data output latency for the different settings of lc[2:0]. synchronous burst with a latency count setting of code 4 will result in zero wa it state; however, a latency count setting of code 5 will cause 1 wa it state (code 6 will cause 2 wai t states, and code 7 will cause 3 wait states) after every four words, regardless of whether a 16-word boundary is crossed. if cr.[9] (data hold) bit is set (data hold of two clocks) this wai t condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent wai t states. 15 read mode (rm) 0 = synchronous burst-mode read 1 = asynchronous page-mode read (default) 14 reserved (r) reserved bits should be cleared (0) 13:11 latency count (lc[2:0]) 010 =code 2 011 =code 3 100 =code 4 101 =code 5 110 =code 6 111 =code 7 (default) (other bit settings are reserved) 10 wait polarity (wp) 0 =wait signal is active low 1 =wait signal is active high (default) 9 data hold (dh) 0 =data held for a 1-clock data cycle 1 =data held for a 2-clock data cycle (default) 8wait delay (wd) 0 =wait de-asserted with valid data 1 =wait de-asserted one data cycle before valid data (default) 7burst sequence (bs) 0 =reserved 1 =linear (default) 6 clock edge (ce) 0 = falling edge 1 = rising edge (default) 5:4 reserved (r) reserved bits should be cleared (0) 3burst wrap (bw) 0 =wrap; burst accesses wrap within burst length set by bl[2:0] 1 =no wrap; burst accesses do not wrap within burst length (default) 2:0 burst length (bl[2:0]) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =continuous-word burst (default) (other bit settings are reserved) note: latency code 2, data hold for a 2-clock data cycle (dh = 1) wait must be de-asserted with valid data (wd = 0). latency code 2, data hold for a 2-cock data cycle (dh=1) wait de-asserted one data cycle before valid data (wd = 1) combination is not supported. table 7. read configuration register description (sheet 2 of 2)
28f640l30, 28f128l30, 28f256l30 datasheet 25 refer to table 8, ?lc and frequency support for bin 1 tavqv/tchqv (85ns / 17ns)? on page 25 and table 9, ?lc and frequency support for bin 2 tavqv/tchqv (110ns / 20ns)? on page 26 for latency code settings. figure 4.first-access latency count code 1 (reserved code 6 code 5 code 4 code 3 code 2 code 0 (reserved) code 7 valid address valid output valid output valid output valid output valid output valid out put valid output valid output valid output valid output valid output valid output valid out put valid output valid output valid output valid output valid output valid out put valid output valid output valid output valid output valid out put valid output valid output valid output valid out put valid output valid output valid out put valid output valid output valid output valid output valid output address [a] adv# [v] dq 15-0 [d/q] clk [c] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] table 8. lc and frequency support for bin 1 t avqv /t chqv (85ns / 17ns) latency count settings frequency support (mhz) 2 27 3 40 4, 5, 6, or 7 52
28f640l30, 28f128l30, 28f256l30 26 datasheet see figure 5, ?example latency count setting using code 3 . 4.3.3 wait polarity the wai t polarity bit (wp), rcr[10] determines the asserted level (v oh or v ol ) of wa it. when wp is set, wai t is asserted-high (default). when wp is cleared, wa i t is asserted-low. wa i t changes state on valid clock edges during active bus cycles (ce# asserted, oe# asserted, rst# deasserted). 4.3.3.1 wait signal function the wai t signal indicates data valid when the device is operating in synchronous mode (cr[15]=0). the wa i t signal is only ?de-asserted? when data is valid on the bus. when the device is operating in synchronous non-array read mode, such as read status, read id, or read query. the wa i t signal is also ?de-asserted? when data is valid on the bus. when the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, wa i t is set to a de-asserted state as determined by cr[10]. see figure 14, ?asynchronous single-word read (adv# latch)? on page 57 , and figure 15, ?asynchronous page-mode read timing? on page 57 . table 9. lc and frequency support for bin 2 t avqv /t chqv (110ns / 20ns) latency count settings frequency support (mhz) 2 22 3 33 4, 5, 6, or 7 40 figure 5.example latency count setting using code 3 clk ce# adv# a[max:0] d[15:0] t data code 3 address data 012 34 r103 high-z
28f640l30, 28f128l30, 28f256l30 datasheet 27 4.3.4 data hold for burst read operations, the data hold (dh) bit determines whether the data output remains valid on d[15:0] for one or two clock cycles. this period of time is called the ? data cycle ?. when dh is set, output data is held for two clocks (default). when dh is cleared, output data is held for one clock (see figure 6 ). the processor?s data setup time and the flash memory?s clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. a method for determining the data hold configuration is shown below: to set the device at one clock data hold for subsequent reads, the following condition must be satisfied: t chqv (ns) + t data (ns) one clk period (ns) t data = data set up to clock (defined by cpu) for example, with a clock frequency of 40 mhz, the clock period is 25 ns. assuming t chqv = 20 ns and t data = 4ns. applying these values to the formula above: 20 ns + 4 ns 25 ns the equation is satisfied and data will be available at every clock period with data hold setting at one clock. if t chqv (ns) + t data (ns) > one clk period (ns), data hold setting of 2 clock periods must be used. table 10. wait summary table condition wait ce# = v ih ce# = v il high-z active oe# = v ih oe# = v il high-z active synchronous array reads active synchronous non-array reads active all asynchronous reads and all writes de-asserted note: active: wait is asserted until data becomes valid, then de-asserts figure 6.data hold timing valid output valid output valid output valid output valid output clk [c] d[15:0] [q] d[15:0] [q] 2 clk data hold 1 clk data hold
28f640l30, 28f128l30, 28f256l30 28 datasheet 4.3.5 wait delay the wai t delay (wd) bit controls the wa i t assertion-delay behavior during synchronous burst reads. wa i t can be asserted either during or one data cycle before valid data is output on dq[15:0]. when wd is set, wa it is de-asserted one data cycle before valid data (default). when wd is cleared, wai t is de-asserted during valid data. 4.3.6 burst sequence the burst sequence (bs) bit selects linear-burst sequence (default). only linear-burst sequence is supported. table 11 shows the synchronous burst sequence for all burst lengths, as well as the effect of the burst wrap (bw) setting. 4.3.7 clock edge the clock edge (ce) bit selects either a rising (default) or falling clock edge for clk. this clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert wai t. 4.3.8 burst wrap the burst wrap (bw) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. when bw is set, burst wrapping does not occur (default). when bw is cleared, burst wrapping occurs. when performing synchronous burst reads with bw set (no wrap), an output delay may occur when the burst sequence crosses its first device-row (16-word) boundary. if the burst sequence?s start address is 4-word aligned, then no delay occurs. if the start address is at the end of a 4-word table 11.burst sequence word ordering start addr. (dec) burst wrap (rcr[3]) burst addressing sequence (dec) 4-word burst (bl[2:0] = 0b001) 8-word burst (bl[2:0] = 0b010) 16-word burst (bl[2:0] = 0b011) continuous burst (bl[2:0] = 0b111) 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4?14-15 0-1-2-3-4-5-6-? 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5?15-0 1-2-3-4-5-6-7-? 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6?15-0-1 2-3-4-5-6-7-8-? 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7?15-0-1-2 3-4-5-6-7-8-9-? 40 4-5-6-7-0-1-2-3 4-5-6-7-8?15-0-1-2-3 4-5-6-7-8-9-10? 50 5-6-7-0-1-2-3-4 5-6-7-8-9?15-0-1-2-3-4 5-6-7-8-9-10-11? 60 6-7-0-1-2-3-4-5 6-7-8-9-10?15-0-1-2-3-4-5 6-7-8-9-10-11-12-? 70 7-0-1-2-3-4-5-6 7-8-9-10?15-0-1-2-3-4-5-6 7-8-9-10-11-12-13? ? ? ? ? ? ? 14 0 14-15-0-1-2?12-13 14-15-16-17-18-19-20-? 15 0 15-0-1-2-3?13-14 15-16-17-18-19-20-21-? ? ? ? ? ? ? 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4?14-15 0-1-2-3-4-5-6-? 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5?15-16 1-2-3-4-5-6-7-? 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6?16-17 2-3-4-5-6-7-8-? 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7?17-18 3-4-5-6-7-8-9-? 41 4-5-6-7-8-9-10-11 4-5-6-7-8?18-19 4-5-6-7-8-9-10? 51 5-6-7-8-9-10-11-12 5-6-7-8-9?19-20 5-6-7-8-9-10-11? 61 6-7-8-9-10-11-12-13 6-7-8-9-10?20-21 6-7-8-9-10-11-12-? 71 7-8-9-10-11-12-13-14 7-8-9-10-11?21-22 7-8-9-10-11-12-13? ? ? ? ? ? ? 14 1 14-15-16-17-18?28-29 14-15-16-17-18-19-20-? 15 1 15-16-17-18-19?29-30 15-16-17-18-19-20-21-?
28f640l30, 28f128l30, 28f256l30 datasheet 29 boundary, the worst case output delay is one clock cycle less than the first access latency count. this delay can take place only once, and doesn?t occur if the burst sequence does not cross a device-row boundary. wa i t informs the system of this delay when it occurs. 4.3.9 burst length the burst length bit (bl[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. the burst lengths are 4-word, 8-word, 16-word, and continuous word. continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see table 11, ?burst sequence word ordering? on page 28 ). when a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the ?burstable? address space.
28f640l30, 28f128l30, 28f256l30 30 datasheet 5.0 programming operations the device supports three programming methods: word programming (40h/10h), buffered programming (e8h, d0h), and buffered enhanced factory programming (buffered efp) (80h, d0h). see section 3.0, ?device operations? on page 17 for details on the various programming commands issued to the device. successful programming requires the addressed block to be unlocked. if the block is locked down, wp# must be deasserted and the block must be unlocked before attempting to program the block. attempting to program a locked block causes a program error (sr[4] and sr[1] set) and termination of the operation. see section 7.0, ?security modes? on page 38 for details on locking and unlocking blocks. the following sections describe device programming in detail. 5.1 word programming wo rd programming operations are initiated by writing the word program setup command to the device (see section 3.0, ?device operations? on page 17 ). this is followed by a second write to the device with the address and data to be programmed. the partition accessed during both write cycles outputs status register data when read. the partition accessed during the second cycle (the data cycle) of the program command sequence is the location where the data is written. see figure 30, ?word program flowchart? on page 74 . programming can occur in only one partition at a time; all other partitions must be in a read state or in erase suspend. v pp must be above v pplk , and within the specified v ppl min/max values (nominally 1.8 v). during programming, the write state machine (wsm) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. programming the flash memory array changes ?ones? to ?zeros.? memory array bits that are zeros can be changed to ones only by erasing the block (see section 6.0, ?erase operations? on page 36 ). the status register can be examined for programming progress and errors by reading any address within the partition that is being programmed. the partition remains in the read status register state until another command is written to that partition. issuing the read status register command to another partition address sets that partition to the read status register state, allowing programming progress to be monitored at that partition?s address. status register bit sr[7] indicates the programming status while the sequence executes. commands that can be issued to the programming partition during programming are program suspend, read status register, read device identifier, cfi query, and read array (this returns unknown data). when programming has finished, status register bit sr[4] (when set) indicates a programming failure. if sr[3] is set, the wsm could not perform the word programming operation because v pp was outside of its acceptable limits. if sr[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow, when word programming has completed.
28f640l30, 28f128l30, 28f256l30 datasheet 31 5.1.1 factory word programming factory word programming is similar to word programming in that it uses the same commands and programming algorithms. however, factory word programming enhances the programming performance with v pp = v pph . this can enable faster programming times during oem manufacturing processes. factory word programming is not intended for extended use. see section 11.2, ?operating conditions? on page 52 for limitations when v pp = v pph . note: when v pp = v ppl , the device draws programming current from the v cc supply. if v pp is driven by a logic signal, v ppl must remain above v ppl min to program the device. when v pp = v pph , the device draws programming current from the v pp supply. figure 7, ?example vpp supply connections? on page 35 shows examples of device power supply configurations. 5.2 buffered programming the device features a 32-word buffer to enable optimum programming performance. for buffered programming, data is first written to an on-chip write buffer. then the buffer data is programmed into the flash memory array in buffer-size increments. this can improve system programming performance significantly over non-buffered programming. when the buffered programming setup command is issued (see section 3.2, ?device commands? on page 18 ), status register information is updated and reflects the availability of the buffer. sr[7] indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. to retry, issue the buffered programming setup command again, and re-check sr[7]. when sr[7] is set, the buffer is ready for loading. (see figure 32, ?buffered program flowchart? on page 76 ). on the next write, a word count is written to the device at the buffer address. this tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. on the next write, a device start address is given along with the first data to be written to the flash memory array. subsequent writes provide additional device addresses and data. all data addresses must lie within the start address plus the word count. optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (a[4:0] = 0x00). a misaligned starting address doubles the total program time. after the last data is written to the buffer, the buffered programming confirm command must be issued to the original block address. the wsm begins to program buffer contents to the flash memory array. if a command other than the buffered programming confirm command is written to the device, a command sequence error occurs and status register bits sr[7,5,4] are set. if an error occurs while writing to the array, the device stops programming, and status register bits sr[7,4] are set, indicating a programming failure. reading from another partition is allowed while data is being programmed into the array from the write buffer (see figure 38, ?read while buffered programming flowchart? on page 82 ). when buffered programming has completed, an additional buffer writes can be initiated by issuing another buffered programming setup command and repeating the buffered program sequence. buffered programming may be performed with v pp = v ppl or v pph (see section 11.2, ?operating conditions? on page 52 for limitations when operating the device with v pp = v pph ). when status register bits sr[5,4] are set, the device does not accept buffered program commands. if an attempt is made to program past an erase-block boundary using the buffered program command, the device aborts the operation. this generates a command sequence error, and status register bits sr[5,4] are set.
28f640l30, 28f128l30, 28f256l30 32 datasheet if buffered programming is attempted while v pp is below v pplk , status register bits sr[4,3] are set. if any errors are detected that have set status register bits, the status register should be cleared using the clear status register command. 5.3 buffered enhanced factory programming buffered enhanced factory programing (buffered efp) speeds up multi-level cell (mlc) flash programming for today's beat-rate-sensitive manufacturing environments. the enhanced programming algorithm used in buffered efp eliminates traditional programming elements that drive up overhead in device programmer systems. buffered efp consists of three phases: setup, program/verify, and exit (see figure 33, ?buffered efp flowchart? on page 77 ). it uses a write buffer to spread mlc program performance across 32 data words. verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. a single two-cycle command sequence programs the entire block of data. this enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. host programmer bus cycles fill the device?s write buffer followed by a status check. sr[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. following the buffer-to-flash array programming sequence, the write state machine (wsm) increments internal addressing to automatically select the next 32-word array boundary. this aspect of buffered efp saves host programming equipment the address-bus setup overhead. with adequate continuity testing, programming equipment can rely on the wsm?s internal verification to ensure that the device has programmed properly. this eliminates the external post- program verification and its associated overhead. 5.3.1 buffered efp requirements and considerations buffered efp requirements: ? ambient temperature: t a = 25 c, 5 c ? v cc within specified operating range. ? vpp driven to v pph . ? target block unlocked before issuing the buffered efp setup and confirm commands. ? the first-word address (wa0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired. ? wa 0 must align with the start of an array buffer boundary 1 . buffered efp considerations: ? for optimum performance, cycling must be limited below 100 erase cycles per block 2 . ? buffered efp programs one block at a time; all buffer data must fall within a single block 3 . ? buffered efp cannot be suspended. ? programming to the flash memory array can occur only when the buffer is full 4 .
28f640l30, 28f128l30, 28f256l30 datasheet 33 ? read operation while performing buffered efp is not supported. notes: 1. word buffer boundaries in the array are determined by a[4:0] (0x00 through 0x1f). the alignment start point is a[4:0] = 0x00. 2. some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. if the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. if the number of words is less than 32, remaining locations must be filled with 0xffff. 5.3.2 buffered efp setup phase after receiving the buffered efp setup and confirm command sequence, status register bit sr[7] (ready) is cleared, indicating that the wsm is busy with buffered efp algorithm startup. a delay before checking sr[7] is required to allow the wsm enough time to perform all of its setups and checks (block-lock status, v pp level, etc.). if an error is detected, sr[4] is set and buffered efp operation terminates. if the block was found to be locked, sr[1] is also set. sr[3] is set if the error occurred due to an incorrect v pp level. note: reading from the device after the buffered efp setup and confirm command sequence outputs status register data. do not issue the read status register command; it will be interpreted as data to be loaded into the buffer. 5.3.3 buffered efp program/verify phase after the buffered efp setup phase has completed, the host programming system must check sr[7,0] to determine the availability of the write buffer for data streaming. sr[7] cleared indicates the device is busy and the buffered efp program/verify phase is activated. sr[0] indicates the write buffer is available. two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. for buffered efp, the count value for buffer loading is always the maximum buffer size of 32 words. during the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. programming of the buffer contents to the flash memory array starts as soon as the buffer is full. if the number of words is less than 32, the remaining buffer locations must be filled with 0xffff. caution: the buffer must be completely filled for programming to occur. supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. any data previously loaded into the buffer during the fill cycle is not programmed into the array. the starting address for data entry must be buffer size aligned, if not the buffered efp algorithm will be aborted and the program fail (sr[4]) flag will be set. data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. the host programming system must poll sr[0] to determine when the buffer program sequence completes. sr[0] cleared indicates that all buffer data has been transferred to the flash array; sr[0] set indicates that the buffer is not available yet for the next fill cycle. the host system may check full status for errors at any time, but it is only necessary on a block basis after buffered efp exit. after the buffer fill cycle, no write cycles should be issued to the device until sr.0 = 0 and the device is ready for the next buffer fill.
28f640l30, 28f128l30, 28f256l30 34 datasheet note: any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. the host programming system continues the buffered efp algorithm by providing the next group of data words to be written to the buffer. alternatively, it can terminate this phase by changing the block address to one outside of the current block?s range. the program/verify phase concludes when the programmer writes to a different block address; data supplied must be 0xffff. upon program/verify phase completion, the device enters the buffered efp exit phase. 5.3.4 buffered efp exit phase when sr[7] is set, the device has returned to normal operating conditions. a full status check should be performed on the partition being programmed at this time to ensure the entire block programmed successfully. when exiting the buffered efp algorithm with a block address change, the read mode of both the programmed and the addressed partition will not change. after buffered efp exit, any valid command can be issued to the device. 5.4 program suspend issuing the program suspend command while programming suspends the programming operation. this allows data to be accessed from memory locations other than the one being programmed. the program suspend command can be issued to any device address; the corresponding partition is not affected. a program operation can be suspended to perform reads only. additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see figure 31, ?program suspend/resume flowchart? on page 75 ). when a programming operation is executing, issuing the program suspend command requests the wsm to suspend the programming algorithm at predetermined points. the partition that is suspended continues to output status register data after the program suspend command is issued. programming is suspended when status register bits sr[7,2] are set. suspend latency is specified in section 12.3, ?program and erase characteristics? on page 64 . to read data from blocks within the suspended partition, the read array command must be issued to that partition. read array, read status register, read device identifier, cfi query, and program resume are valid commands during a program suspend. a program operation does not need to be suspended in order to read data from a block in another partition that is not programming. if the other partition is already in a read array, read device identifier, or cfi query state, issuing a valid address returns corresponding read data. if the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. during a program suspend, deasserting ce# places the device in standby, reducing active current. v pp must remain at its programming level, and wp# must remain unchanged while in program suspend. if rst# is asserted, the device is reset.
28f640l30, 28f128l30, 28f256l30 datasheet 35 5.5 program resume the resume command instructs the device to continue programming, and automatically clears status register bits sr[7,2]. this command can be written to any partition. when read at the partition that?s programming, the device outputs data corresponding to the partition?s last state. if error bits are set, the status register should be cleared before issuing the next instruction. rst# must remain deasserted (see figure 31, ?program suspend/resume flowchart? on page 75 ). 5.6 program protection when v pp = v il , absolute hardware write protection is provided for all device blocks. if v pp is below v pplk , programming operations halt and sr[3] is set indicating a v pp -level error. block lock registers are not affected by the voltage level on v pp ; they may still be programmed and read, even if v pp is less than v pplk . figure 7.example vpp supply connections factory word programming with v pp = v pph complete write/erase protection when v pp < v pplk low voltage and factory word programming low voltage programming only full device protection unavailable low voltage programming only logic control of device protection v cc v pp prot# vcc vpp vcc vpp 10 k ? vcc vpp vcc vpp v cc v pp = v pph v cc v cc
28f640l30, 28f128l30, 28f256l30 36 datasheet 6.0 erase operations flash erasing is performed on a block basis. an entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. when a block is erased, all bits within that block read as logical ones. the following sections describe block erase operations in detail. 6.1 block erase block erase operations are initiated by writing the block erase setup command to the address of the block to be erased (see section 3.2, ?device commands? on page 18 ). next, the block erase confirm command is written to the address of the block to be erased. erasing can occur in only one partition at a time; all other partitions must be in a read state. if the device is placed in standby (ce# deasserted) during an erase operation, the device completes the erase operation before entering standby.v pp must be above v pplk and the block must be unlocked (see figure 34, ?block erase flowchart? on page 78 ). during a block erase, the write state machine (wsm) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. erasing the flash memory array changes ?zeros? to ?ones.? memory array bits that are ones can be changed to zeros only by programming the block (see section 5.0, ?programming operations? on page 30 ). the status register can be examined for block erase progress and errors by reading any address within the partition that is being erased. the partition remains in the read status register state until another command is written to that partition. issuing the read status register command to another partition address sets that partition to the read status register state, allowing erase progress to be monitored at that partition?s address. sr[0] indicates whether the addressed partition or another partition is erasing. the partition?s status register bit sr[7] is set upon erase completion. status register bit sr[7] indicates block erase status while the sequence executes. when the erase operation has finished, status register bit sr[5] indicates an erase failure if set. sr[3] set would indicate that the wsm could not perform the erase operation because v pp was outside of its acceptable limits. sr[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow once the block erase operation has completed. 6.2 erase suspend issuing the erase suspend command while erasing suspends the block erase operation. this allows data to be accessed from memory locations other than the one being erased. the erase suspend command can be issued to any device address; the corresponding partition is not affected. a block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see figure 31, ?program suspend/resume flowchart? on page 75 ).
28f640l30, 28f128l30, 28f256l30 datasheet 37 when a block erase operation is executing, issuing the erase suspend command requests the wsm to suspend the erase algorithm at predetermined points. the partition that is suspended continues to output status register data after the erase suspend command is issued. block erase is suspended when status register bits sr[7,6] are set. suspend latency is specified in section 12.3, ?program and erase characteristics? on page 64 . to read data from blocks within the suspended partition (other than an erase-suspended block), the read array command must be issued to that partition first. during erase suspend, a program command can be issued to any block other than the erase-suspended block. block erase cannot resume until program operations initiated during erase suspend complete. read array, read status register, read device identifier, cfi query, and erase resume are valid commands during erase suspend. additionally, clear status register, program, program suspend, block lock, block unlock, and block lock-down are valid commands during erase suspend. to read data from a block in a partition that is not erasing, the erase operation does not need to be suspended. if the other partition is already in read array, read device identifier, or cfi query, issuing a valid address returns corresponding data. if the other partition is not in a read state, one of the read commands must be issued to the partition before data can be read. during an erase suspend, deasserting ce# places the device in standby, reducing active current. v pp must remain at a valid level, and wp# must remain unchanged while in erase suspend. if rst# is asserted, the device is reset. 6.3 erase resume the erase resume command instructs the device to continue erasing, and automatically clears status register bits sr[7,6]. this command can be written to any partition. when read at the partition that?s erasing, the device outputs data corresponding to the partition?s last state. if status register error bits are set, the status register should be cleared before issuing the next instruction. rst# must remain deasserted (see figure 31, ?program suspend/resume flowchart? on page 75 ). 6.4 erase protection when v pp = v il , absolute hardware erase protection is provided for all device blocks. if v pp is below v pplk , erase operations halt and sr[3] is set indicating a v pp -level error.
28f640l30, 28f128l30, 28f256l30 38 datasheet 7.0 security modes the device features security modes used to protect the information stored in the flash memory array. the following sections describe each security mode in detail. 7.1 block locking individual instant block locking is used to protect user code and/or data within the flash memory array. all blocks power up in a locked state to protect array data from being altered during power transitions. any block can be locked or unlocked with no latency. locked blocks cannot be programmed or erased; they can only be read. software-controlled security is implemented using the block lock and block unlock commands. hardware-controlled security can be implemented using the block lock-down command along with asserting wp#. also, v pp data security can be used to inhibit program and erase operations (see section 5.6, ?program protection? on page 35 and section 6.4, ?erase protection? on page 37 ). 7.1.1 lock block to lock a block, issue the lock block setup command. the next command must be the lock block command issued to the desired block?s address (see section 3.2, ?device commands? on page 18 and figure 36, ?block lock operations flowchart? on page 80 ). if the set read configuration register command is issued after the block lock setup command, the device configures the rcr instead. block lock and unlock operations are not affected by the voltage level on v pp . the block lock bits may be modified and/or read even if v pp is below v pplk . 7.1.2 unlock block the unlock block command is used to unlock blocks (see section 3.2, ?device commands? on page 18 ). unlocked blocks can be read, programmed, and erased. unlocked blocks return to a locked state when the device is reset or powered down. if a block is in a lock-down state, wp# must be deasserted before it can be unlocked (see figure 8, ?block locking state diagram? on page 39 ). 7.1.3 lock-down block a locked or unlocked block can be locked-down by writing the lock-down block command sequence (see section 3.2, ?device commands? on page 18 ). blocks in a lock-down state cannot be programmed or erased; they can only be read. however, unlike locked blocks, their locked state cannot be changed by software commands alone. a locked-down block can only be unlocked by issuing the unlock block command with wp# deasserted. to return an unlocked block to locked- down state, a lock-down command must be issued prior to changing wp# to v il . locked-down blocks revert to the locked state upon reset or power up the device (see figure 8, ?block locking state diagram? on page 39 ).
28f640l30, 28f128l30, 28f256l30 datasheet 39 7.1.4 block lock status the read device identifier command is used to determine a block?s lock status (see section 9.2, ?read device identifier? on page 48 ). data bits d[1:0] display the addressed block?s lock status; d0 is the addressed block?s lock bit, while d1 is the addressed block?s lock-down bit. 7.1.5 block locking during suspend block lock and unlock changes can be performed during an erase suspend. to change block locking during an erase operation, first issue the erase suspend command. monitor the status register until sr[7] and sr[6] are set, indicating the device is suspended and ready to accept another command. next, write the desired lock command sequence to a block, which changes the lock state of that block. after completing block lock or unlock operations, resume the erase operation using the erase resume command. figure 8.block locking state diagram [000] [001] [011] [111] [101] [110] [100] 60h/ d0h 60h/01h 60h/ 2fh 6 0 h / 2 f h 60h/d0h 60h/ 01h 60h/ d0h 60h/ 01h 60h/ 2fh 60h/ 2fh unlocked locked wp# = v il = 0 wp# = v ih = 1 power-up/reset default power-up/reset default 60h/d0h = unlock command 60h/01h = lock command 60h/2fh = lock-down command locked-down locked-down is disabled by wp# = v ih
28f640l30, 28f128l30, 28f256l30 40 datasheet note: a lock block setup command followed by any command other than lock block, unlock block, or lock-down block produces a command sequence error and set status register bits sr[4] and sr[5]. if a command sequence error occurs during an erase suspend, sr[4] and sr[5] remains set, even after the erase operation is resumed. unless the status register is cleared using the clear status register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. if a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. however, the erase operation completes when it is resumed. block lock operations cannot occur during a program suspend. see appendix a, ?write state machine (wsm)? on page 67 , which shows valid commands during an erase suspend. 7.2 protection registers the device contains 17 protection registers (prs) that can be used to implement system security measures and/or device identification. each protection register can be individually locked. the first 128-bit protection register is comprised of two 64-bit (8-word) segments. the lower 64- bit segment is pre-programmed at the factory with a unique 64-bit number. the other 64-bit segment, as well as the other sixteen 128-bit protection registers, are blank. users can program these registers as needed. when programmed, users can then lock the protection register(s) to prevent additional bit programming (see figure 9, ?protection register map? on page 41 ). the user-programmable protection registers contain one-time programmable (otp) bits; when programmed, register bits cannot be erased. each protection register can be accessed multiple times to program individual bits, as long as the register remains unlocked. each protection register has an associated lock register bit. when a lock register bit is programmed, the associated protection register can only be read; it can no longer be programmed. additionally, because the lock register bits themselves are otp, when programmed, lock register bits cannot be erased. therefore, when a protection register is locked, it cannot be unlocked
28f640l30, 28f128l30, 28f256l30 datasheet 41 . 7.2.1 reading the protection registers the protection registers can be read from within any partition?s address space. to read the protection register, first issue the read device identifier command at any partitions? address to place that partition in the read device identifier state (see section 3.2, ?device commands? on page 18 ). next, perform a read operation at that partition?s base address plus the address offset corresponding to the register to be read. table 14, ?device identifier information? on page 49 shows the address offsets of the protection registers and lock registers. register data is read 16 bits at a time. note: if a program or erase operation occurs within the device while it is reading a protection register, certain restrictions may apply. see table 12, ?simultaneous operation restrictions? on page 46 for details. figure 9.protection register map 0x89 lock register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x102 0x109 0x8a 0x91 128-bit protection register 16 (user-programmable) 128-bit protection register 1 (user-programmable) 0x88 0x85 64-bit segment (user-programmable) 0x84 0x81 0x80 lock register 0 64-bit segment (factory-programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit protection register 0
28f640l30, 28f128l30, 28f256l30 42 datasheet 7.2.2 programming the protection registers to program any of the protection registers, first issue the program protection register command at the parameter partition?s base address plus the offset to the desired protection register (see section 3.2, ?device commands? on page 18 ). next, write the desired protection register data to the same protection register address (see figure 9, ?protection register map? on page 41 ). the device programs the 64-bit and 128-bit user-programmable protection register data 16 bits at a time (see figure 37, ?protection register programming flowchart? on page 81 ). issuing the program protection register command outside of the protection register?s address space causes a program error (sr[4] set). attempting to program a locked protection register causes a program error (sr[4] set) and a lock error (sr[1] set). note: if a program or erase operation occurs when programming a protection register, certain restrictions may apply. see table 12, ?simultaneous operation restrictions? on page 46 for details. 7.2.3 locking the protection registers each protection register can be locked by programming its respective lock bit in the lock register. to lock a protection register, program the corresponding bit in the lock register by issuing the program lock register command, followed by the desired lock register data (see section 3.2, ?device commands? on page 18 ). the physical addresses of the lock registers are 0x80 for register 0 and 0x89 for register 1. these addresses are used when programming the lock registers (see table 14, ?device identifier information? on page 49 ). bit 0 of lock register 0 is already programmed at the factory, locking the lower, pre-programmed 64-bit region of the first 128-bit protection register containing the unique identification number of the device. bit 1 of lock register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit protection register. the other bits in lock register 0 are not used. lock register 1 controls the locking of the upper sixteen 128-bit protection registers. each of the 16 bits of lock register 1 correspond to each of the upper sixteen 128-bit protection registers. programming a bit in lock register 1 locks the corresponding 128-bit protection register. caution: after being locked, the protection registers cannot be unlocked.
28f640l30, 28f128l30, 28f256l30 datasheet 43 8.0 dual-operation considerations the multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. 8.1 memory partitioning the l30 flash memory array is divided into multiple 8-mbit partitions, which allows simultaneous read-while-write operations. simultaneous program and erase is not allowed. only one partition at a time can be in program or erase mode. the flash device supports read-while-write operations with bus cycle granularity and not command granularity. in other words, it is not assumed that both bus cycles of a two cycle command (an erase command for example) will always occur as back to back bus cycles to the flash device. in practice, code fetches (reads) may be interspersed between write cycles to the flash device, and they will likely be directed to a different partition than the one being written. this is especially true when a processor is executing code from one partition that instructs the processor to program or erase in another partition. 8.2 read-while-write command sequences when issuing commands to the device, a read operation can occur between 2-cycle write command?s ( figure 10 , and figure 11 ). however, a write operation issued between a 2-cycle commands write sequence causes a command sequence error. (see figure 12 ) when reading from the same partition after issuing a setup command, status register data is returned, regardless of the read mode of the partition prior to issuing the setup command. . figure 10. operating mode with correct command sequence example partition a partition a partition b 0x20 0xd0 0xff a ddress [a] we# [w] oe# [g] data [d/q]
28f640l30, 28f128l30, 28f256l30 44 datasheet 8.2.1 simultaneous operation details the l30 flash memory device supports simultaneous read from one partition while programming or erasing in any other partition. certain features like the protection registers and query data have special requirements with respect to simultaneous operation capability. these will be detailed in the following sections. 8.2.2 synchronous and asynchronous read-while-write characteristics and waveforms this section describes the transitions of write operation to asynchronous read, and synchronous read to write operation. 8.2.2.1 write operation to asynchronous read transition w18 - t whav the ac parameter w18 (t whav -we# high to address valid) is required when transitioning from a write cycle (we# going high) to perform an asynchronous read (only address valid is required). w19 and w20 - t whcv and t whvh the ac parameters w19 or w20 (t whcv -we# high to clock valid, and t whvh - we# high to adv# high) is required when transitioning from a write cycle (we# going high) to perform a synchronous burst read. a delay from we# going high to a valid clock edge or adv# going high to latch a new address must be met. figure 11. operating mode with correct command sequence example partition a partition b partition a 0x20 valid array data 0xd0 a ddress [a] we# [w] oe# [g] data [d/q] figure 12. operating mode with illegal command sequence example partition a partition b partition a partition a 0x20 0xff 0xd0 sr[7:0] a ddress [a] we# [w] oe# [g] data [d/q]
28f640l30, 28f128l30, 28f256l30 datasheet 45 8.2.2.2 synchronous read to write operation transition w21 - t vhwl w22 - t chwl the ac parameters w21 (t vhwl - adv# high to we# low) and w22 (t chwl -clock high to we# low) are required when the device is in a synchronous mode and clock is active. a write bus cycle consists of two parts: ? the host provides an address to the flash device; and ? the host then provides data to the flash device. the flash device in turn binds the received data with the received address. when operating synchronously (rcr.15 = 0), the address of a write cycle may be provided to the flash by the first active clock edge with adv# low, or rising edge of adv# as long as the applicable cycle separation conditions are met between each cycle. if neither a clock edge nor a rising adv# edge is used to provide a new address at the beginning of a write cycle (the clock is stopped and adv# is low), the address may also be provided to the flash device by holding the address bus stable for the required amount of time (w5, t av w h ) before the rising we# edge. alternatively, the host may choose not to provide an address to the flash device during subsequent write cycles (if adv# is high and only ce# or we# is toggled to separate the prior cycle from the current write cycle). in this case, the flash device will use the most recently provided address from the host. refer to figure 22, ?write to asynchronous read timing? on page 62 , figure 23, ?synchronous read to write timing? on page 62 , and figure 24, ?write to synchronous read timing? on page 63 , for representation of these timings. 8.2.3 read operation during buffered programming flowchart the multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. to perform a read while buffered programming operation, first issue a buffered program set up command in a partition. when a read operation occurs in the same partition after issuing a setup command, status register data will be returned, regardless of the read mode of the partition prior to issuing the setup command. to read data from a block in other partition and the other partition already in read array mode, a new block address must be issued. however, if the other partition is not already in read array mode, issuing a read array command will cause the buffered program operation to abort and a command sequence error would be posted in the status register. see figure 38, ?read while buffered programming flowchart? on page 82 for more details. note: simultaneous read-while-buffered efp is not supported.
28f640l30, 28f128l30, 28f256l30 46 datasheet 8.3 simultaneous operation restrictions since the l30 flash memory device supports simultaneous read from one partition while programming or erasing in another partition, certain features like the protection registers and cfi query data have special requirements with respect to simultaneous operation capability. ( table 12 provides details on restrictions during simultaneous operations.) table 12.simultaneous operation restrictions protection register or cfi data parameter partition array data other partitions notes read (see notes) write/erase while programming or erasing in a main partition, the protection register or cfi data may be read from any other partition. reading the parameter partition array data is not allowed if the protection register or query data is being read from addresses within the parameter partition. (see notes) read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers or cfi data from parameter partition addresses is not allowed when reading array data from the parameter partition. read read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers or cfi data in a partition that is different from the one being programed/erased, and also different from the parameter partition is allowed. write no access allowed read while programming the protection register, reads are only allowed in the other main partitions. access to array data in the parameter partition is not allowed. programming of the protection register can only occur in the parameter partition, which means this partition is in read status. no access allowed write/erase read while programming or erasing the parameter partition, reads of the protection registers or cfi data are not allowed in any partition. reads in partitions other than the main partitions are supported.
28f640l30, 28f128l30, 28f256l30 datasheet 47 9.0 special read states the following sections describe non-array read states. non-array reads can be performed in asynchronous read or synchronous burst mode. a non-array read operation occurs as asynchronous single-word mode. when non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. when a non-array read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. each partition can be in one of its read states independent of other partitions? modes. see figure 13, ?asynchronous single-word read (adv# low)? on page 56 , figure 14, ?asynchronous single-word read (adv# latch)? on page 57 , and figure 16, ?synchronous single-word array or non-array read timing? on page 58 for details. 9.1 read status register the status of any partition is determined by reading the status register from the address of that particular partition. to read the status register, issue the read status register command within the desired partition?s address range. status register information is available at the partition address to which the read status register, wo rd program, or block erase command was issued. status register data is automatically made available following a wo rd program, block erase, or block lock command sequence. reads from a partition after any of these command sequences outputs that partition?s status until another valid command is written to that partition (e.g. read array command). the status register is read using single asynchronous-mode or synchronous burst mode reads. status register data is output on d[7:0], while 0x00 is output on d[15:8]. in asynchronous mode the falling edge of oe#, or ce# (whichever occurs first) updates and latches the status register contents. however, reading the status register in synchronous burst mode, ce# or adv# must be toggled to update status data. the status register read operations do not affect the read state of the other partitions. the device write status bit (sr[7]) provides overall status of the device. the partition status bit (sr[0]) indicates whether the addressed partition or some other partition is actively programming or erasing. status register bits sr[6:1] present status and error information about the program, erase, suspend, v pp , and block-locked operations. table 13. status register description (sheet 1 of 2) status register (sr) default value = 0x80 device write status erase suspend status erase status program status v pp status program suspend status block- locked status partition status dws ess es ps vpps pss bls pws 76543210 bit name description 7 device write status (dws) 0 = device is busy; program or erase cycle in progress; sr[0] valid. 1 = device is ready; sr[6:1] are valid. 6 erase suspend status (ess) 0 = erase suspend not in effect. 1 = erase suspend in effect.
28f640l30, 28f128l30, 28f256l30 48 datasheet always clear the status register prior to resuming erase operations. avoids status register ambiguity when issuing commands during erase suspend. if a command sequence error occurs during an erase-suspend state, the status register contains the command sequence error status (sr[7,5,4] set). when the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the status register because it contains the previous error status. 9.1.1 clear status register the clear status register command clears the status register, leaving all partition read states unchanged. it functions independent of v pp . the write state machine (wsm) sets and clears sr[7,6,2,0], but it sets bits sr[5:3,1] without clearing them. the status register should be cleared before starting a command sequence to avoid any ambiguity. a device reset also clears the status register. 9.2 read device identifier the read device identifier command instructs the addressed partition to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data when that partition?s addresses are read (see section 3.2, ?device commands? on page 18 for details on issuing the read device identifier command). table 14, ?device identifier information? on page 49 and table 15, ?device id codes? on page 49 show the address offsets and data values for this device. issuing a read device identifier command to a partition that is programming or erasing places that partition in the read identifier state while the partition continues to program or erase in the background. 5erase status (es) 0 = erase successful. 1 = erase fail or program sequence error when set with sr[4,7]. 4program status (ps) 0 = program successful. 1 = program fail or program sequence error when set with sr[5,7] 3v pp status (vpps) 0 = vpp within acceptable limits during program or erase operation. 1 = vpp < vpplk during program or erase operation. 2 program suspend status (pss) 0 = program suspend not in effect. 1 = program suspend in effect. 1 block-locked status (bls) 0 = block not locked during program or erase. 1 = block locked during program or erase; operation aborted. 0 partition write status (pws) dws pw s 0 0 = program or erase operation in addressed partition. 0 1 = program or erase operation in other partition. 1 0 = no active program or erase operations. 1 1 = reserved. (non-buffered efp operation. for buffered efp operation, see section 5.3, ?buffered enhanced factory programming? on page 32 ). table 13.status register description (sheet 2 of 2) status register (sr) default value = 0x80
28f640l30, 28f128l30, 28f256l30 datasheet 49 9.3 cfi query the cfi query command instructs the device to output common flash interface (cfi) data when partition addresses are read. see section 3.2, ?device commands? on page 18 for details on issuing the cfi query command. appendix c, ?common flash interface? on page 83 shows cfi information and address offsets within the cfi database. issuing the cfi query command to a partition that is programming or erasing places that partition?s outputs in the cfi query state, while the partition continues to program or erase in the background. the cfi query command is subject to read restrictions dependent on parameter partition availability, as described in table 12, ?simultaneous operation restrictions? on page 46 . table 14. device identifier information item address (1,2) data manufacturer code pba + 0x00 0089h device id code pba + 0x01 id (see ta bl e 15 ) block lock configuration: bba + 0x02 lock bit: ? block is unlocked dq 0 = 0b0 ? block is locked dq 0 = 0b1 ? block is not locked-down dq 1 = 0b0 ? block is locked-down dq 1 = 0b1 configuration register pba + 0x05 configuration register data lock register 0 pba + 0x80 pr-lk0 64-bit factory-programmed protection register pba + 0x81?0x84 factory protection register data 64-bit user-programmable protection register pba + 0x85?0x88 user protection register data lock register 1 pba + 0x89 protection register data 128-bit user-programmable protection registers pba + 0x8a?0x109 pr-lk1 notes: 1. pba = partition base address. 2. bba = block base address. table 15. device id codes id code type device density device identifier codes ?t (top parameter) ?b (bottom parameter) device code 64 mbit 8811 8814 128 mbit 8812 8815 256 mbit 8813 8816
28f640l30, 28f128l30, 28f256l30 50 datasheet 10.0 power and reset 10.1 power-up/down characteristics power supply sequencing is not required if vcc, vccq, and vpp are connected together; if vccq and/or vpp are not connected to the vcc supply, then v cc should attain v ccmin before applying v ccq and v pp . device inputs should not be driven before supply voltage equals v ccmin . power supply transitions should only occur when rst# is low. this protects the device from accidental programming or erasure during power transitions. 10.2 power supply decoupling flash memory devices require careful power supply de-coupling. three basic power supply current considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks produced when ce# and oe# are asserted and deasserted. when the device is accessed, many internal conditions change. circuits within the device enable charge-pumps, and internal logic states change at high speed. all of these internal activities produce transient signals. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. because intel ? multi-level cell (mlc) flash memory devices draw their power from v cc , vpp, and vccq, each power connection should have a 0.1 f ceramic capacitor connected to a corresponding ground connection (e.g.vccq to vssq). high-frequency, inherently low- inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices used in the system, a 4.7 f electrolytic capacitor should be placed between power and ground close to the devices. the bulk capacitor is meant to overcome voltage droop caused by pcb trace inductance. 10.3 automatic power saving (aps) automatic power saving (aps) provides low power operation during a read?s active state. i ccaps is the average current measured over any 5 ms time interval, 5 s after ce# is deasserted. during aps, average current is measured over the same time interval 5 s after the following events happen: (1) there is no internal read, program or erase operations cease; (2) ce# is asserted; (3) the address lines are quiescent and at v ssq or v ccq . oe# may also be driven during aps. 10.4 reset characteristics asserting rst# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization may not occur. this is because the flash memory may be providing status information, instead of array data as expected. connect rst# to the same active-low reset signal used for cpu initialization.
28f640l30, 28f128l30, 28f256l30 datasheet 51 also, because the device is disabled when rst# is asserted, it ignores its control inputs during power-up/down. invalid bus conditions are masked, providing a level of memory protection. system designers should guard against spurious writes when v cc voltages are above v lko . because both we# and ce# must be asserted for a write operation, deasserting either signal inhibits writes to the device. the command user interface (cui) architecture provides additional protection because alteration of memory contents can only occur after successful completion of a two-step command sequence (see section 3.2, ?device commands? on page 18 ).
28f640l30, 28f128l30, 28f256l30 52 datasheet 11.0 thermal and dc characteristics 11.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. 11.2 operating conditions warning: operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. parameter maximum rating notes temperature under bias ?25 c to +85 c storage temperature ?65 c to +125 c voltage on any signal (except vcc, vpp) ?0.5 v to +3.8 v 1 vpp voltage ?0.2 v to +10v 1,2,3 vcc voltage ?0.2 v to +2.5 v1 vccq voltage ?0.2 v to +3.8 v1 output short circuit current 100 ma 4 notes: 1. voltages shown are specified with respect to v ss . minimum dc voltage is ?0.5 v on input/output signals and ?0.2 v on v cc , v ccq , and v pp . during transitions, this level may undershoot to ?2.0 v for periods <20 ns. maximum dc voltage on v cc is v cc +0.5 v, which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. maximum dc voltage on input/output signals and v ccq is v ccq +0.5 v, which, during transitions, may overshoot to v ccq +2.0 v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0 v for periods <20 ns. 3. program/erase voltage is typically 1.7 v?2.0 v. 9.0 v can be applied for 80 hours maximum total, to any blocks for 1000 cycles maximum. 9.0 v program/erase voltage may reduce block cycling capability. 4. output shorted for no more than one second. no more than one output shorted at a time. symbol parameter min max units notes t c operating temperature ?25 +85 c 1 v cc vcc supply voltage 1.7 2.0 v v ccq i/o supply voltage 2.2 3.3 v ppl v pp voltage supply (logic level) 0.9 2.0 2 v pph factory word programming v pp 8.5 9.5 t pph maximum vpp hours v pp = v pph 80 hours block erase cycles main and parameter blocks v pp = v cc 100,000 cycles main blocks v pp = v pph 1000 parameter blocks v pp = v pph 2500 notes: 1. t c = case temperature 2. in typical operation, the vpp program voltage is vppl. vpp can be connected to 8.50 v ? 9.5 v for 1000 cycles on main blocks, and 2500 cycles on parameter blocks.
28f640l30, 28f128l30, 28f256l30 datasheet 53 11.3 dc current characteristics sym parameter v ccq 2.2 v ? 3.3 v unit test conditions notes typ max i li input load current 2 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd 1 i lo output leakage current d[15:0], wait 10 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i ccs i ccd v cc standby, power down 64 mbit 20 35 a v cc = v cc max v ccq = v ccq max ce# = v ccq rst# = v ccq (for i ccs ) rst# = gnd (for i ccd ) wp# = v ih 1,2 128 mbit 30 55 256 mbit 55 95 i ccaps aps 64 mbit 20 35 a v cc = v cc max v ccq = v ccq max ce# = v ssq rst# = v ccq all inputs are at rail to rail (v ccq or v ssq ). 128 mbit 30 55 256 mbit 55 95 i ccr average v cc read current asynchronous single-word f = 5mhz (1 clk) 14 16 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1 page-mode read f = 13 mhz (5 clk) 9 10 ma 4-word read synchronous burst read f = 40mhz 16 19 ma burst length=4 20 24 ma burst length=8 23 27 ma burst length=16 30 35 ma burst length = continuous synchronous burst read f = 54mhz 18 21 ma burst length=4 24 28 ma burst length=8 28 33 ma burst length=16 30 35 ma burst length = continuous i ccw, i cce v cc program current, v cc erase current 36 51 ma v pp = v ppl , program/erase in progress 1,3,4, 7 26 33 ma v pp = v pph , program/erase in progress 1,3,5, 7 i ccws, i cces v cc program suspend current, v cc erase suspend current 64 mbit 20 35 a ce# = v ccq ; suspend in progress 1,6,3 128 mbit 30 55 256 mbit 55 95 i pps, i ppws, i ppes v pp standby current, v pp program suspend current, v pp erase suspend current 0.2 5 a v pp = v ppl , suspend in progress 1,3
28f640l30, 28f128l30, 28f256l30 54 datasheet 11.4 dc voltage characteristics i ppr v pp read 2 15 a v pp v cc 1,3 i ppw v pp program current 0.05 0.10 ma v pp = v ppl, program in progress 822 v pp = v pph, program in progress i ppe v pp erase current 0.05 0.10 ma v pp = v ppl, erase in progress 822 v pp = v pph, erase in progress notes: 1. all currents are rms unless noted. typical values at typical v cc , t c = +25c. 2. i ccs is the average current measured over any 5 ms time interval 5 s after ce# is deasserted. 3. sampled, not 100% tested. 4. v cc read + program current is the sum of v cc read and v cc program currents. 5. v cc read + erase current is the sum of v cc read and v cc erase currents. 6. i cces is specified with the device deselected. if device is read while in erase suspend, current is i cces plus i ccr . 7. i ccw , i cce measured over typical or max times specified in section 12.3, ?program and erase characteristics? on page 64 sym parameter v ccq 2.2 v ? 3.3 v unit test condition notes min max v il input low voltage 0 0.4 v 1 v ih input high voltage v ccq ?0.4 v ccq v v ol output low voltage 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage v ccq ?0.1 v v cc = v cc min v ccq = v ccq min i oh = ?100 a v pplk v pp lock-out voltage 0.4 v 2 v lko v cc lock voltage 1.0 v v lkoq v ccq lock voltage 0.9 v notes: 1. v il can undershoot to ?0.4v and v ih can overshoot to v ccq +0.4v for durations of 20 ns or less. 2. v pp < v pplk inhibits erase and program operations. do not use v ppl and v pph outside their valid ranges. sym parameter v ccq 2.2 v ? 3.3 v unit test conditions notes typ max
28f640l30, 28f128l30, 28f256l30 datasheet 55 12.0 ac characteristics 12.1 ac read specifications (v ccq = 2.2 v ? 3.3 v) num symbol parameter speed ?85 ?110 units notes min max min max asynchronous specifications r1 t avav read cycle time 85 110 ns 6 r2 t av qv address to output valid 85 110 ns r3 t elqv ce# low to output valid 85 110 ns r4 t glqv oe# low to output valid 25 30 ns 1,2 r5 t phqv rst# high to output valid 150 150 ns 1 r6 t elqx ce# low to output in low-z 0 0 ns 1,3 r7 t glqx oe# low to output in low-z 0 0 ns 1,2,3 r8 t ehqz ce# high to output in high-z 24 24 ns 1,3 r9 t ghqz oe# high to output in high-z 24 24 ns r10 t oh output hold from first occurring address, ce#, or oe# change 00 ns r11 t ehel ce# pulse width high 20 20 ns 1 r12 t eltv ce# low to wait valid 16 20 ns 1 r13 t ehtz ce# high to wait high z1720ns1,3 r15 t gltv oe# low to wait valid 17 20 ns 1 r16 t gltx oe# low to wait in low-z 0 0 ns 1,3 r17 t ghtz oe# high to wait in high-z 20 24 ns 1,3 latching specifications r101 t avvh address setup to adv# high 10 12 ns 1 r102 t elvh ce# low to adv# high 10 12 ns r103 t vlqv adv# low to output valid 85 110 ns r104 t vlvh adv# pulse width low 10 12 ns r105 t vhvl adv# pulse width high 10 12 ns r106 t vhax address hold from adv# high 9 10 ns 1,4 r108 t apa page address access 25 25 ns 1 r111 t phvh rst# high to adv# high 30 30 ns 1 clock specifications r200 f clk clk frequency 52 40 mhz 1,3 r201 t clk clk period 19.2 25 ns r202 t ch/cl clk high/low time 9 9 ns r203 t fclk/rclk clk fall/rise time 3 3 ns synchronous specifications r301 t avch/l address setup to clk 9 9 ns 1 r302 t vlch/l adv# low setup to clk 9 9 ns r303 t elch/l ce# low setup to clk 9 9 ns r304 t chqv / t clqv clk to output valid 17 20 ns r305 t chqx output hold from clk 3 3 ns 1,5 r306 t chax address hold from clk 10 10 ns 1,4,5 r307 t chtv clk to wait valid 20 22 ns 1,5
28f640l30, 28f128l30, 28f256l30 56 datasheet l note: wait shown de-asserted during asynchronous read mode (cr[10]=0 wait asserted low). r311 t chvl clk valid to adv# setup 0 0 ns 1 r312 t chtx wait hold from clk 3 3 ns 1,5 notes: 1. see figure 26, ?ac input/output reference waveform? on page 65 for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv . 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax , whichever timing specification is satisfied first. 5. applies only to subsequent synchronous reads. figure 13. asynchronous single-word read (adv# low) num symbol parameter speed ?85 ?110 units notes min max min max r5 r7 r6 r17 r15 r9 r4 r8 r3 r1 r2 r1 a d d re ss [a] adv# ce# [e} oe# [g] wait [t] data [d/q] rst # [p]
28f640l30, 28f128l30, 28f256l30 datasheet 57 note: wait shown de-asserted during asynchronous read mode (cr[10]=0 wait asserted low). note: wait shown de-asserted during asynchronous read mode (cr[10]=0 wait asserted low) figure 14. asynchronous single-word read (adv# latch) r10 r7 r6 r17 r15 r9 r4 r8 r3 r106 r101 r105 r105 r2 r1 a ddress [a] a[1:0][a] adv# ce# [e} oe# [g] wait [t] data [d/q] figure 15. asynchronous page-mode read timing r108 r9 r7 r17 r15 r10 r4 r8 r3 r106 r101 r105 r105 r1 r1 r2 a [max:2] [a] a[1:0] adv# ce# [e] oe# [g] wait [t] data [d/q]
28f640l30, 28f128l30, 28f256l30 58 datasheet notes: 1. wait is driven per oe# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. this diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by ce# deassertion after the first word in the burst. figure 16. synchronous single-word array or non-array read timing latency count r312 r305 r304 r4 r17 r307 r15 r9 r7 r8 r303 r102 r3 r104 r106 r101 r104 r105 r105 r2 r306 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q] figure 17. continuous burst read, showing an output delay timing r305 r305 r305 r305 r304 r4 r7 r312 r307 r15 r303 r102 r3 r106 r105 r105 r101 r2 r304 r304 r304 r306 r302 r301 clk [c] a d d re ss [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
28f640l30, 28f128l30, 28f256l30 datasheet 59 note: at the end of word line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. note: wait is driven per oe# assertion during synchronous array or non-array read. wait asserted during initial latency and deasserted during valid data (cr.10 = 0 wait asserted low). notes: 1. clk can be stopped in either high or low state. 2. wait is driven per oe# assertion during synchronous array or non-array read. wait asserted during initial latency and deasserted during valid data (cr.10 = 0 wait asserted low). figure 18. synchronous burst-mode four-word read timing latency count a q0 q1 q2 q3 r3 07 r10 r304 r3 05 r3 04 r4 r7 r17 r1 5 r9 r8 r30 3 r3 r106 r102 r105 r105 r101 r2 r3 06 r302 r30 1 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q] figure 19. burst suspend timing q0 q1 q1 q2 r15 r17 r304 r304 r7 r6 r312 r15 r4 r9 r4 r3 r106 r101 r105 r105 r1 r1 r2 r305 r305 r304 clk a d d re ss [a] adv# ce# [e] oe# [g] wait [t] we# [w] dat a [d/q]
28f640l30, 28f128l30, 28f256l30 60 datasheet 12.2 ac write specifications nbr. symbol parameter (1, 2) min max units notes w1 t phwl rst# high recovery to we# low 150 ns 1,2,3 w2 t elwl ce# setup to we# low 0 ns 1,2,3 w3 t wlwh we# write pulse width low 50 ns 1,2,4 w4 t dvwh data setup to we# high 50 ns 1,2 w5 t av wh address setup to we# high 50 ns w6 t wheh ce# hold from we# high 0 ns w7 t whdx data hold from we# high 0 ns w8 t whax address hold from we# high 0 ns w9 t whwl we# pulse width high 20 ns 1,2,5 w10 t vpwh v pp setup to we# high 200 ns 1,2,3,7 w11 t qvvl v pp hold from status read 0 ns w12 t qvbl wp# hold from status read 0 ns 1,2,3,7 w13 t bhwh wp# setup to we# high 200 ns w14 t whgl we# high to oe# low 0 ns 1,2,9 w16 t whqv we# high to read valid t avqv +35 ns 1,2,3,6,10 write to asynchronous read specifications w18 t whav we# high to address valid 0 ns 1,2,3,6 write to synchronous read specifications w19 t whch/l we# high to clock valid 19 ns 1,2,3,6,10 w20 t whvh we# high to adv# high 19 ns synchronous read to write specifications w21 t vhwl adv# high to we# low 20 ns 1,2,3,11 w22 t chwl clock high to we# low 20 ns notes: 1. write timing characteristics during erase suspend are the same as write-only operations. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). hence, t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl or t ehel ) is defined from ce# or we# high (whichever occurs first) to ce# or we# low (whichever occurs last). hence, t whwl = t ehel = t whel = t ehwl ). 6. t whvh or t whch/l must be met when transitioning from a write cycle to a synchronous burst read. 7. v pp and wp# should be at a valid level until erase or program success is determined. 8. this specification is only applicable when transitioning from a write cycle to an asynchronous read. see spec w19 and w20 for synchronous read. 9. when doing a read status operation following a program or erase write cycle, w14 is 20ns. 10.add 10ns if the write operations results in a rcr or block lock status change, for the subsequent read operation to reflect this change. 11.these specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
28f640l30, 28f128l30, 28f256l30 datasheet 61 note: wait de-asserted during asynchronous read and during write. wait high-z during write per oe# de- asserted. figure 20. write to write timing figure 21. asynchronous read to write timing w1 w7 w4 w7 w4 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w8 w8 w5 w5 a d d re ss [a] ce# [e} we# [w] oe# [g] data [d/q] rst # [p] q d r5 w7 w4 r10 r7 r6 r17 r15 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 a d d re ss [a] ce# [e} oe# [g] we# [w] wait [t] data [d/q] rst # [p]
28f640l30, 28f128l30, 28f256l30 62 datasheet note: wait shown de-asserted and high-z per oe# de-assertion during write operation (cr[10]=0 wait asserted low). clock is ignored during write operation. figure 22. write to asynchronous read timing d q w1 r9 r8 r4 r3 r2 w7 w4 r17 r15 w14 w1 8 w3 w3 r10 w6 w2 r1 r1 w8 w5 a ddress [a] adv# [v] ce# [e} we# [w] oe# [g] wait [t] data [d/q] rst # [p] figure 23. synchronous read to write timing latency count q d d w7 r3 05 r304 r7 r312 r307 r1 6 w1 5 w9 w19 w8 w9 w3 w3 w2 r8 r4 w6 r11 r1 3 r11 r30 3 r3 w2 0 r10 4 r10 4 r106 r102 r105 r105 w18 w5 r101 r2 r3 06 r302 r30 1 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] we# wait [t] data [d/q]
28f640l30, 28f128l30, 28f256l30 datasheet 63 note: wait shown de-asserted and high-z per oe# de-assertion during write operation (cr[10]=0 wait asserted low). figure 24. write to synchronous read timing latency count d q q w1 r304 r305 r304 r3 w7 w4 r307 r15 r4 w1 8 w3 w3 r11 r303 r11 w6 w2 r104 r106 r104 r306 w8 w5 r302 r301 r2 clk a ddress [a] adv# ce# [e} we# [w] oe# [g] wait [t] data [d/q] rst # [p]
28f640l30, 28f128l30, 28f256l30 64 datasheet 12.3 program and erase characteristics 12.4 reset specifications nbr. symbol parameter v ppl v pph units notes min typ max min typ max conventional word programming w200 t prog/w program time single word 150 tbd 150 tbd s 1 single cell 30 tbd 30 tbd buffered programming w200 t prog/w program time single word 150 tbd 150 tbd s 1 w251 t buff one buffer (32 words) 640 tbd 288 864 buffered enhanced factory programming w451 t befp/w program single word n/a n/a n/a n/a 7 21 s 1,2 w452 t befp/ setup buffered efp setup n/a n/a n/a 5 n/a n/a 1 erasing and suspending w500 t ers/pb erase time 16-kword parameter 0.4 2.5 0.4 2.5 s 1 w501 t ers/mb 64-kword main 0.8 4 0.7 4 w600 t susp/p suspend latency program suspend 2025 2025 s w601 t susp/e erase suspend 2025 2025 notes: 1. typical values measured at t c = +25 c and nominal voltages. performance numbers are valid for all speed versions. excludes system overhead. sampled, but not 100% tested. 2. averaged over entire device. nbr. symbol parameter min max unit notes p1 t plph rst# pulse width low 100 ns 1,2,3,4 p2 t plrh rst# low to device reset during erase 25 s 1,3,4,7 rst# low to device reset during program 25 1,3,4,7 p3 t vccph v cc power valid to rst# de-assertion (high) 60 1,4,5,6 notes: 1. these specifications are valid for all device versions (packages and speeds). 2. the device may reset if t plph is = v cc min. 6. if rst# is tied to any supply/signal with v ccq voltage levels, the rst# input voltage must not exceed v cc until v cc >= v cc (min). 7. reset completes within t plph if rst# is asserted while no erase or program operation is executing.
28f640l30, 28f128l30, 28f256l30 datasheet 65 12.5 ac test conditions note: ac test inputs are driven at v ccq for logic "1" and 0.0 v for logic "0." input/output timing begins/ends at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed occurs at v cc = v cc min. notes: 1. see the following table for component values. 2. test configuration component value for worst case speed conditions. 3. c l includes jig capacitance . figure 25. reset operation waveforms figure 26. ac input/output reference waveform ( a) reset during read mode (b) reset during program or block erase p1 p2 (c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v v cc (d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5 reset wmf o input v ccq /2 v ccq /2 output v ccq 0v test points figure 27. transient equivalent testing load circuit device under test r 2 r 1 v ccq out c l table 16. test configuration component value for worst case speed conditions test configuration c l (pf) r 1 ( ? )r 2 ( ? ) 2.0 v standard test 30 22k 22k
28f640l30, 28f128l30, 28f256l30 66 datasheet 12.6 capacitance figure 28. clock input ac waveform table 17.capacitance symbol parameter 1 typ max unit condition note c in input capacitance 6 8 pf v in = 0.0 v 1,2,3 c out output capacitance 8 12 pf v out = 0.0 v 1,2 c ce# ce# input capacitance 10 12 pf v in = 0.0 v notes: 1. t c = +25c, f = 1 mhz. 2. sampled, not 100% tested. 3. c in (max) = 10pf for 256mbit density clk [c] v ih v il r203 r202 r201 clkinput wmf
28f640l30, 28f128l30, 28f256l30 datasheet 67 appendix a write state machine (wsm) figure 29 shows the command state transitions (next state table) based on incoming commands. only one partition can be actively programming or erasing at a time. each partition stays in its last read state (read array, read device id, cfi query or read status register) until a new command changes it. the next wsm state does not depend on the partition?s output state. figure 29. write state machine ? next state table (sheet 1 of 6) read array (3) wor d pr og r am (4,5) wr ite to buf f ered pr og r am (bp) erase setup (4,5) buffered enhanced fac tor y pg m setup (4) be conf ir m, p/ e res ume, ulb, conf ir m (9) bp / pr g / er a s e suspend read status clear status regis t er (6) read id/quer y lock, unloc k, lock-dow n, cr setup (5) (ffh) (10h/40h) (e8h) (20h) (80h) (d0h) (b0h) (70h) (50h) (90h, 98h) (60h) ready pr og r am setup bp setup er a s e setup befp setup loc k/ cr setup ready (unlock block) setup busy setup busy wor d program suspend suspend wor d pr o g r a m busy setup bp load 1 bp load 2 bp conf ir m bp busy bp busy bp suspend bp suspend bp busy setup erase busy busy erase suspend suspend erase suspend wor d pr og r am setup in erase suspend bp setup in er a s e suspend erase busy loc k/cr setup in erase suspend setup busy wor d program suspend in er a s e suspend suspend wor d pr o g r a m busy in er a s e suspend wor d pr o g r a m suspend bp load 1 {give word count load [n-1]}; if n=0 (w ord count =1) go to bp conf ir m; el s e (n not = 0) go to bp load 2 bp load 2 (give data load) ready (lock error [botch]) otp busy ready (error [botch]) ready (error [botch]) wor d pr o g r a m busy bp conf ir m w hen count=0, else bp load 2 (note: bp w ill botch at this point if any block address is different from the first address) current chip state (8) command in p ut to chi p and resultin g chi p next state bp bp busy lock/cr setup otp ready (lock error [botch]) ready ready wor d pr og r am pr og r am busy word pr og r am suspend wor d program busy wor d pr o g r a m in erase suspend word pr og r am busy in erase suspend wor d pr o g r a m suspend in er a s e suspend word pr og r am busy in erase suspend busy word pr og r am suspend in erase suspend bp suspend ready (error [botch]) er a s e busy ready (error [botch]) er a s e busy bp busy bp suspend er a s e erase suspend erase suspend word pr og r am busy in erase suspend
28f640l30, 28f128l30, 28f256l30 68 datasheet figure 29. write state machine ? next state table (sheet 2 of 6) setup bp load 1 bp load 2 bp conf ir m bp busy in erase suspend bp busy bp suspend in erase suspend bp suspend bp busy in erase suspend erase suspend (unlock block) setup befp loading dat a (x=32) bp load 1 in er as e suspend {give word count load [n-1]}; if n=0 (w ord count =1) go to bp confirm; el s e (n not = 0) go to bp load 2 befp busy buffered enhanced fac t or y pr o g r a m mod e befp pr og r a m and verify busy (if block address given mat c he s address given on befp setup c omman d) . commands treated as data. (7) loc k/ cr setup in er a s e suspend erase suspend (lock error [botch]) bp conf ir m in er as e suspend when count=0, else bp load 2 (note: bp w ill botch at this point if any block address is dif ferent from the first address) bp in erase suspend bp load 2 in erase suspend ( giv e data load ) bp suspend in erase suspend ready (error [botch bp] in erase suspend) bp busy in er as e suspend bp suspend in er a s e suspend bp busy in erase suspend erase suspend (error [botch bp]) erase suspend (lock er r or [botch]) ready (error [botch]) ready (error [botch])
28f640l30, 28f128l30, 28f256l30 datasheet 69 figure 29. write state machine ? next state table (sheet 3 of 6) read array (3) wor d program setup (4,5) bp setup erase setup (4,5) buffered enhanced factory pg m setup (4) be con f i r m, p/ e res ume, ulb conf irm (9) pr o g r a m/ er a s e suspend read status clear status register (6) read id/query lock, unloc k, lock-dow n, cr setup (5) (ffh) (10h/40h) (e8h) (20h) (30h) (d0h) (b0h) (70h) (50h) (90h, 98h) (60h) status rea d status read status rea d c o mman d input to chip and resulting output mux next state ready, erase suspend, bp suspend status read lock/cr setup, lock/cr setup in erase susp output mu x does not change. befp setup, befp pgm & verify busy, erase setup, otp setup, bp: setup , load 1, load 2, confirm, word pgm setup, word pgm setup in erase susp, bp setup, load1, load 2, confirm in erase suspend current chip sta te status read output mu x does not change. status read id read otp busy bp busy, word program busy, erase busy, bp busy bp busy in erase suspend word pgm suspend, word pgm busy in erase suspend, pgm suspend in erase suspend read a rray
28f640l30, 28f128l30, 28f256l30 70 datasheet figure 29. write state machine ? next state table (sheet 4 of 6) otp setup (5) lock block confirm (9 ) lock-dow n block confirm (9 ) write cr confirm (9 ) block address (wa0) illegal cmds or befp data (2) (c0h) (01h) (2fh) (03h) (xxxxh) (all other codes) otp setup ready (lock er r o r [botch]) read y (lock block) re ad y (lock dow n blk) read y (set cr) ready n/a ready exit ready ready erase suspend n/a word program suspend in erase suspend bp confirm w hen count=0, el s e bp load 2 (note: bp w ill botch at this point if any block address is different from the first address) word pr o g r a m suspend bp load 1 {give word count load [n-1]}; if n=0 (w ord count =1) go to bp confirm; els e (n not = 0) go to bp load 2 bp load 2 (give data load) otp bus y ready (error [botch]) word program busy word program busy wsm operation completes command input to chip and resultin g chip next state n/a ready (lock error [botch]) ready bp busy bp suspend ready (error [botch]) erase busy word program busy in erase suspend busy n/a n/a n/a erase suspend word program busy in erase suspend
28f640l30, 28f128l30, 28f256l30 datasheet 71 figure 29. write state machine ? next state table (sheet 5 of 6) exit erase suspend erase suspend (lock er r o r [botch]) erase suspend (lock block) erase suspend (lock dow n block) erase suspend (set cr) befp program and verify busy (if block address given matches address given on befp setup command). commands treated as data. (7) bp load 1 in erase suspend {give word count load [n-1]}; if n=0 (w ord count =1) go to bp con f ir m; els e n ? 0 go to bp load 2 n/a ready bp conf irm in erase suspend w hen count=0, el se bp load 2 (note: bp will botch at this point if any block address is diff erent from the first address) bp load 2 in erase suspend ( give data load ) befp busy ready erase suspend (lock er r o r [botch]) n/a ready (error [botch bp] in erase suspend) bp busy in er a s e suspend bp suspend in erase suspend ready (error [botch])
28f640l30, 28f128l30, 28f256l30 72 datasheet figure 29. write state machine ? next state table (sheet 6 of 6) notes: 1. the "partition data when read" field shows what the user will read from the flash chip after issuing the appropriate command given the partition address is not changed from the address given during the command. "read-while-write" functionality gives more flexibility in data output from the device. the data read from the chip depends on the partition address applied to the device; each partition is placed into one of 3 otp setup (5) lock block confirm (9 ) lock-dow n block confirm (9 ) write cr confirm (9 ) block address (wa0) illegal cmds or befp data (2) ( c0h) ( 01h) ( 2fh) (03h) ( ffffh) (all other codes) status read status read status read c ommand input to chip and resulting output mux next state wsm operation completes output mux does not change. a rray read status read array read output mux does not change. output mux does not change.
28f640l30, 28f128l30, 28f256l30 datasheet 73 possible output states during commands: read array, read status or read id/cfi, depending on the command given to the chip; this partition's output state is retained until a new command is given to the chip at that partition address; for example, this allows the user to set partition #1's output state to read array, and partition #4's output state to read status; every time the partition address is changed to partition #4 (without issuing a new command), the status will be read from the chip. 2. "illegal commands" include commands outside of the allowed command set (allowed commands: 40h [pgm], 20h [erase], etc.) 3. if a "read array" is attempted from a busy partition, the result will be "garbage" data. the key point is that the output mux for that partition will be pointing to the "array", but garbage data will be output. when the user returns to this partition address some time in the future, the output mux will be in the "read array" state from its last visit. "read id" and "read query" commands do the exact same thing in the device. the id and query data are located at different locations in the address map. 4. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. 5. the 2nd cycle of the following 2 cycle commands will be ignored by the user interface: program setup, erase setup, otp setup and lock/unlock/lock-down/cr setup when issued in an "illegal condition". illegal conditions are such as "pgm setup while busy", "erase setup while busy", etc. 6. the clear status command only clears the error bits in the status register if the device is not in the following modes: wsm running (pgm busy, erase busy, pgm busy in erase suspend, otp busy, befp modes). 7. befp writes are only allowed when the status register bit #0 = 0, or else the data is ignored. 8. the "current state" is that of the "chip" and not of the "partition"; each partition "remembers" which output (array, id/cfi or status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. 9. confirm commands (lock block, unlock block, lock-down block, configuration register) perform the operation and then move to the ready state. 10.all two cycle commands will be considered as a contiguous whole during device suspend states. individual commands will not be parsed separately. thus for example the second cycle of an erase command issued in program suspend will not resume the program operation.
28f640l30, 28f128l30, 28f256l30 74 datasheet appendix b flowcharts figure 30. word program flowchart program suspend loop start wr i te 0x40, wor d address wr i te data, wor d address read status register sr[7] = full status check (if desir ed) program complete suspend? 1 0 no yes word program procedure repeat for subsequent wor d program operations. full status register check can be done after each program, or after a sequence of program oper ations. wr i te 0xff after the last operation to set to the read array state. comments bus operation command data =0x40 addr = locati on to program wr i te program setup data = data to program addr = locati on to program wr i te data status register data read none check sr[7] 1 =wsm ready 0 =wsm busy idle none (setup) (confirm) full status check procedure read status register program successful sr[3] = sr[1] = 0 0 sr[4] = 0 1 1 1 v pp range error device protect error program error sr[3] must be cleared before the wr ite state machine will allow further program attempts. if an err or is detected, clear the status register before continuing operations - only the clear staus register command clears the status register error bits. idle idle bus operation none none command check sr[3]: 1 =v pp error check sr[4]: 1 = data program er ror comments idle none check sr[1]: 1 = block locked; operation aborted
28f640l30, 28f128l30, 28f256l30 datasheet 75 figure 31. program suspend/resume flowchart read status register sr.7 = sr.2 = wr ite ffh susp partition read array data program completed done reading wr ite ffh pgm' d partition wr ite d0h any address program resumed read array data 0 no 0 yes 1 1 program suspend / resume procedure wr i te program resume data =d0h addr = suspended block (ba) bus operation command comments wr i te program suspend data =b0h addr = block to suspend (ba) standby check sr.7 1 =wsm r eady 0 =wsm busy standby check sr.2 1 = program suspended 0 = program completed wr i te read array data =ffh addr =any address within the suspended partition read read arr ay data from bl ock other than the one being progr ammed read status register data addr = suspended block (ba) pgm_sus.wmf start wr ite b0h any address program suspend read status program resume read array read array wr ite 70h same partition wr i te read status data =70h addr = same partition if the suspended partition was placed in read array mode: wr i te read status return partition to status mode: data =70h addr = same partition wr ite 70h same partition read status
28f640l30, 28f128l30, 28f256l30 76 datasheet figure 32. buffered program flowchart start get next target address issue buffer prog. cmd. 0xe8, block address read status register at block address write buffer available? sr[7] = 1 = yes device supports buffer writes? set timeout or loop counter timeout or count expired? write confirm 0xd0 and block address yes no buffer program data, start address x = 0 yes 0 = no yes use single word programming abort buffer program? no x = n? write buffer data, block address x = x + 1 write to another block address buffer program aborted no yes yes write word count, block address suspend program loop read status register sr[7] =? full status check if desired program complete suspend program? 1 0 yes no issue read status register command no 1. word count value on d[7:0] is loaded into the word count register. count ranges for this device are n = 0x00 to 0x1f. 2. the device outputs the status register when read. 3. write buffer contents will be programmed at the device star t address or destination flash address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a[4:0] of the start address = 0x00). 5. the device aborts the buffer program command if the current address is outside the original block address. 6. the status register indicates an improper command sequence if the buffer program command is aborted; use the clear status register command to clear error bits. full status check can be done after all erase and write sequences complete. write 0xff after the last operation to place the partition in the read array state. bus operation standby read command none none write buffer prog. setup read none idle none comments check sr[7]: 1 = wsm ready 0 = wsm busy status register data addr = block address data = 0xe8 addr = block address sr[7] = valid addr = block address check sr[7]: 1 = write buffer available 0 = no write buffer available write (notes 5, 6) buffer prog. conf. data = 0xd0 addr = block address write (notes 1, 2) none data = n-1 = word count n = 0 corresponds to count = 1 addr = block address write (notes 3, 4) none data = write buffer data addr = start address write (notes 5, 6) none data = write buffer data addr = block address buffer programming procedure
28f640l30, 28f128l30, 28f256l30 datasheet 77 figure 33. buffered efp flowchart wri t e data @ 1 st wo rd address last data? wri t e 0xffff, address not within current block program done? read status reg. y no (s r[7]=0) full status check procedure program complete read status reg. befp exited? yes (sr[7]=1) start wri te 0x80 @ 1 st wo rd address v pp applied, block unlocked wri te 0xd0 @ 1 st wo rd address befp setup done? read status reg. exit n program & verify phase exit phase setup phase buffered enhanced factory programming (buffered-efp) procedure x = 32? initialize count: x = 0 increment count: x = x+1 y notes: 1. first-word address to be programmed within the target block must be aligned on a write-buffer boundary. 2. write-buffer contents are programmed sequentially to the flash array starting at the first word address; ws m internally increments addressing. n check v pp , lock e rrors (sr[3,1]) yes (s r[7]=0) comments bus state operation befp setup delay data stream ready? read status reg. no (s r[0]=1) repeat for subsequent blocks; after befp exit, a full status register check ca n determine if any program error occurred; see full status register check procedure in the word program flowchart. wri te 0xff to enter read array state. check sr[7]: 0 = exit not completed 1 = exit completed check exit status read status register data = status reg. data address = 1st wo rd addr befp exit standby if sr[7] is set, check: sr[3] set = v pp e rror sr[1] set = locked block error condition check standby check sr[7]: 0 = befp ready 1 = befp not ready befp setup done? standby data = status reg. data address = 1 st word addr status register read data = 0x80 @ 1 st word address befp confirm wri te data = 0x80 @ 1 st word address befp setup wri te (note 1) v pph applied to vpp unlock block wri te befp setup bus state comments operation no (s r[0]=1) yes (s r[0]=0) no (s r[7]=1) yes (s r[0]=0) befp program & verify comments bus state operation wri t e (note 2) load buffer standby increment count standby initialize count data = data to program address = 1 st word addr. x = x+1 x = 0 standby buffer full? x = 32? yes = read sr[0] no = load next data word read standby status register data stream ready? data = status register data address = 1 st word addr. check sr[0]: 0 = ready for data 1 = not ready for data read standby standby wri t e status register program done? last data? exit prog & verify phase data = status reg. data address = 1 st word addr. check sr[0]: 0 = program done 1 = program in progress no = fill buffer again yes = exit data = 0xffff @ address not in current block
28f640l30, 28f128l30, 28f256l30 78 datasheet figure 34. block erase flowchart start full erase status check procedure repeat for subsequent bl ock er asur es. full status register check can be done after each bl ock erase or after a sequence of block erasures. wr i te 0xff after the last operation to enter read array mode. sr[1,3] must be cleared before the wr ite state machine will allow further erase attempts. only the clear status register command clears sr[1, 3, 4, 5]. if an err or is detected, clear the status register before attempting an erase retry or other error recovery. no suspend erase 1 0 0 0 1 1,1 1 1 0 yes suspend erase loop 0 wr i te 0x20, block address wr i te 0xd 0, block address read status register sr[7] = full erase status check (if desir ed) block erase complete read status register block erase successful sr[1] = block locked error block erase procedure bus operation command comments wr i te block erase setup data =0x20 addr = block to be erased (ba) wr i te erase confirm data =0xd0 addr = block to be erased (ba) read none status register data. idle none check sr[7]: 1 =wsm r eady 0 =wsm busy bus operation command comments sr[3] = v pp range error sr[4,5] = command sequence error sr[5] = block erase error idle none check sr[3]: 1 =v pp range error idle none check sr[4,5]: both 1 = command sequence error idle none check sr[5]: 1 = block erase error idle none check sr[1]: 1 = attempted erase of locked block; er ase aborted. (b l ock erase) (erase confirm)
28f640l30, 28f128l30, 28f256l30 datasheet 79 figure 35. erase suspend/resume flowchart erase completed read array data 0 0 no read 1 program program loop read array data 1 start read status regi ster sr[7] = sr[6] = erase resumed read or program? done wr i te wr i te idle idle wr i te erase suspend read array or program none none program resume data =0xb0 addr = sam e partition address as above data = 0xff or 0x40 addr =any address within the suspended par ti tion check sr[7]: 1 =wsm ready 0 =wsm busy check sr[6]: 1 =erase suspended 0 =erase completed data =0xd0 addr =any address bus operation command comments read none status register data. addr = sam e partition read or wr i te none read array or program data from/to block other than the one being erased erase suspend / resume procedure if the suspended partition was placed in read array mode or a program loop: wr ite 0xb0, any address (erase suspend) wr ite 0x70, same partition (read status) wr ite 0xd0, any address (erase resume) wr ite 0x70, same partition (read status) wr i te 0xff , er ased partition (read array) wr i te read status data =0x70 addr =any partition address wr i te read status regi ster return partition to status mode: data =0x70 addr = sam e partition
28f640l30, 28f128l30, 28f256l30 80 datasheet figure 36. block lock operations flowchart no start write 0x60, block address write 0x90 read block lock status locking change? lock change complete write either 0x01/0xd0/0x2f, block address write 0xff partition address yes write write write (optional) read (optional) idle write lock setup lock, unlock, or lock-down confirm read device id block lock status none read array data =0x60 addr =block to lock/unlock/lock-down data =0x01 (block lock) 0xd0 (block unlock) 0x2f (lock-down block) addr =block to lock/unlock/lock-down data =0x90 addr =block address + offset 2 block lock status data addr =block address + offset 2 confirm locking change on d[1,0]. data =0xff addr =block address bus operation command comments locking operations procedure (lock confirm) (read device id) (read array) optional (lock setup)
28f640l30, 28f128l30, 28f256l30 datasheet 81 figure 37. protection register programming flowchart full status check procedure program protection register operation addresses must be within the protection register address space. addr esses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each program, or after a sequence of program oper ations. wr i te 0xff after the last operation to set read array state. sr[3] must be cleared befor e the wr i te state machine will allow further program attempts. only the clear staus register command clears sr[1, 3, 4]. if an err or is detected, clear the status register before attempting a program retry or other error recovery. 1 0 1 1 1 protection register programming procedure start wr i te 0xc 0, pr address wr i te pr address & data read status register sr[7] = full status check (if desir ed) program complete read status register data program successful sr[3] = sr[4] = sr[1] = v pp range er ror pr ogram error register locked; program aborted idle idle bus operation none none command check sr[3]: 1 =v pp range error check sr[4]: 1 = programming error comments wr i te wr i te idle program pr setup protection program none data = 0xc0 addr = first location to program data = data to program addr = location to program check sr[7]: 1 = wsm ready 0 = wsm busy bus operation command comments read none status register data. idle none check sr[1]: 1 =block locked; oper ation aborted (program setup) (confirm data) 0 0 0
28f640l30, 28f128l30, 28f256l30 82 datasheet figure 38. read while buffered programming flowchart start get next target address issue buffered program command e8h and block address read status register (at block address) set timeout or loop counter write confirm d0h and block address write buffer data, start address x = 0 abort buffered program? no x = n? write buffer data, block address x = x + 1 write to another block address buffered program aborted yes yes write word count, block address 1. word count values on dq 0 -dq 7 are loaded into the count register. count ranges for this device are n = 0000h to 0001f h 2. the device outputs the status register when read, or the device outputs array data when read from block in other partition (toggle oe# to update array data). 3. write buffer contents will be programmed at the device star t address or destination flash address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a 4 ?a 0 of the start address = 0). 5. the device aborts the buffered program command if the current address is outside the original block address. 6. the status register indicates an "improper command sequence" if the buffered program command is aborted. follo w this with a clear status register command. 7. a new write cycle command to read must be preceded wit h a confirm command. 8. if a read array operation occurs in a partition other than the one being programmed, that is not in read array mode, a rea d array command must be written. full status check can be done after all erase and write sequences complete. write ffh after the last operation to res e the partition to read array mode. bus operation read write (note 7, and 8) command read array read array write buffered program read standby comments check sr.7 1 = wsm ready 0 = wsm busy data = ffh addr = newblock address data = e8h addr = block address status register data sr.7 = valid addr = block address check sr.7 1 = device wsm is busy 0 = device wsm is ready write program confirm data = d0h addr = block address write (notes 1, 2) data = n-1 = word count n = 0 corresponds to count = 1 addr = block address write (notes 3, 4) data = write buffer data addr = start address write (notes 5, 6) data = write buffer data addr = block address sr.7 =? full status check if desired program complete 1 read array data from block in other partition (new block address) or write ffh to read from a block in other partition? read status? read status register 0 read array? no yes yes read array data no read array data from block in other partition (new block address) or read array data from block in other partition (new block address) or read array data from block in other partition (new block address) or read array data from block in other partition (new block address) no
28f640l30, 28f128l30, 28f256l30 datasheet 83 appendix c common flash interface the common flash interface (cfi) is part of an overall specification for multiple command-set and control-interface descriptions. this appendix describes the database structure containing the data returned by a read operation after issuing the cfi query command (see section 3.2, ?device commands? on page 18 ). system software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. the system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. c.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device?s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq 7-0 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ?q? and ?r,? appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. the device outputs ascii ?q? in the low byte (dq 7-0 ) and 00h in the high byte (dq 15-8 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word-wide devices is always ?00h,? the leading ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table 18. summary of query structure output as a function of device and mode device hex offset hex code ascii v alue 00010: 51 "q" device addresses 00011: 52 "r" 00012: 59 "y"
28f640l30, 28f128l30, 28f256l30 84 datasheet table 19.example of query structure output of x16- devices c.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ?database.? the structure sub-sections and address locations are summarized below. table 20.query structure notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 08000h is block 1?s beginning location when the block size is 16k-word). 3. offset 15 defines ?p? which points to the primary intel-specific extended query table. word addressing: byte addressing: offset hex code v alue offset hex code v alue a x ?a 0 d 15 ? d 0 a x ?a 0 d 7 ? d 0 00010h 0051 "q" 00010h 51 "q" 00011h 0052 "r" 00011h 52 "r" 00012h 0059 "y" 00012h 59 "y" 00013h p_id lo prvendor 00013h p_id lo prvendor 00014h p_id hi id # 00014h p_id lo id # 00015h p lo prvendor 00015h p_id hi id # 00016h p hi tbladr 00016h ... ... 00017h a _id lo a ltvendor 00017h 00018h a _id hi id # 00018h ... ... ... ... offset sub-section nam e descri p tion (1) 00001-fh reserved reserved for vendor-specific information 00010h cfi query identification string command set id and vendor data offset 0001bh system interface information device timing & voltage information 00027h device geometry definition flash device layout p (3) primar y intel-s p ecific extended quer y table vendor-defined additional information specific
28f640l30, 28f128l30, 28f256l30 datasheet 85 c.3 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). table 21. cfi identification table 22. system interface information offset length description add. hex code value 10h 3 query-unique ascii string ?qry? 10: --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interface id code. 13: --03 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --0a 16: --01 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 offset length description add. hex code value 1bh 1 1b: --17 1.7v 1ch 1 1c: --20 2.0v 1dh 1 1d: --85 8.5v 1eh 1 1e: --95 9.5v 1fh 1 ?n? such that t yp ical sin g le word p ro g ram time-out = 2 n -sec 1f: --08 256s 20h 1 ?n? such that t yp ical max. buffer write time-out = 2 n -sec 20: --09 512s 21h 1 ?n? such that t yp ical block erase time-out = 2 n m-sec 21: --0a 1s 22h 1 ?n? such that t yp ical full chi p erase time-out = 2 n m-sec 22: --00 na 23h 1 ?n? such that maximum word p ro g ram time-out = 2 n times t yp ical 23: --01 512s 24h 1 ?n? such that maximum buffer write time-out = 2 n times t yp ical 24: --01 1024s 25h 1 ?n? such that maximum block erase time-out = 2 n times t yp ical 25: --02 4s 26h 1 ?n? such that maximum chi p erase time-out = 2 n times t yp ical 26: --00 na v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts
28f640l30, 28f128l30, 28f256l30 86 datasheet c.4 device geometry definition table 23.device geometry definition offset length description code 27h 1 ?n? such that device size = 2 n in number of bytes 27: see table below 76543210 28h 2 ? ? ? ? x64 x32 x16 x8 28: --01 x16 15 14 13 12 11 10 9 8 ????????29:--00 2ah 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: --06 64 2b: --00 2ch 1 2c: 2dh 4erase block region 1 information 2d: bits 0?15 = y, y+1 = number of identical-size erase blocks 2e: bits 16?31 = z, region erase block(s) size are z x 256 bytes 2f: 30: 31h 4erase block region 2 information 31: bits 0?15 = y, y+1 = number of identical-size erase blocks 32: bits 16?31 = z, region erase block(s) size are z x 256 bytes 33: 34: 35h 4 reserved for future erase block region information 35: 36: 37: 38: see table below see table below see table below see table below flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region address 64 mbit ?b ?t ?b ?t ?b ?t 27:--17--17--18--18--19--19 28:--01--01--01--01--01--01 29:--00--00--00--00--00--00 2a:--06--06--06--06--06--06 2b:--00--00--00--00--00--00 2c:--02--02--02--02--02--02 2d: --03 --3e --03 --7e --03 --fe 2e:--00--00--00--00--00--00 2f:--80--00--80--00--80--00 30:--00--02--00--02--00--02 31: --3e --03 --7e --03 --fe --03 32: --00 --00 --00 --00 --00 --00 33: --00 --80 --00 --80 --00 --80 34: --02 --00 --02 --00 --02 --00 35: --00 --00 --00 --00 --00 --00 36: --00 --00 --00 --00 --00 --00 37: --00 --00 --00 --00 --00 --00 38: --00 --00 --00 --00 --00 --00 128 mbit 256 mbit
28f640l30, 28f128l30, 28f256l30 datasheet 87 c.5 intel-specific extended query table table 24. primary vendor-specific extended query offset (1) length descri p tion hex p = 10ah (optional flash features and commands) add. code v alue (p+0)h 3 primary extended query table 10a --50 "p" (p+1)h unique ascii string ?pri? 10b: --52 "r" (p+2)h 10c: --49 "i" (p+3)h 1 major version number, ascii 10d: --31 "1" (p+4)h 1 minor version number, ascii 10e: --33 "3" (p+5)h 4 optional feature and command support (1=yes, 0=no) 10f: --e6 (p+6)h bits 10?31 are reserved; undefined bits are ?0.? if bit 31 is 110: --03 (p+7)h ?1? then another 31 bit field of o p tional features follows at 111: --00 (p+8)h the end of the bit?30 field. 112: --00 bit 0 chip erase supported bit 0 = 0no bit 1 suspend erase supported bit 1 = 1yes bit 2 suspend program supported bit 2 = 1yes bit 3 legacy lock/unlock supported bit 3 = 0no bit 4 queued erase supported bit 4 = 0no bit 5 instant individual block locking supported bit 5 = 1yes bit 6 protection bits supported bit 6 = 1yes bit 7 pagemode read supported bit 7 = 1yes bit 8 synchronous read supported bit 8 = 1yes bit 9 simultaneous operations supported bit 9 = 1yes (p+9)h 1 113: --01 bit 0 pro g ram su pp orted after erase sus p end bit 0 = 1yes (p+a)h 2block status register mask 114: --03 (p+b)h bits 2?15 are reserved; undefined bits are ?0? 115: --00 bit 0 block lock-bit status register active bit 0 = 1yes bit 1 block lock-down bit status active bit 1 = 1yes (p+c)h 1 116: --18 1.8v (p+d)h 1 117: --90 9.0v supported functions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? v cc logic supply highest performance program/erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts
28f640l30, 28f128l30, 28f256l30 88 datasheet table 25.protection register information table 26.burst read information offset (1) length descri p tion hex p = 10ah (optional flash features and commands) add. code v alue (p+e)h 1 118: --02 2 (p+f)h 4 protection field 1: protection description 119: --80 80h (p+10)h this field describes user-available one time pro g rammable 11a: --00 00h (p+11)h ( otp ) protection re g ister b y tes. some are p re- p ro g rammed 11b: --03 8 byte (p+12)h 11c: --03 8 byte (p+13)h 10 protection field 2: protection description 11d: --89 89h (p+14)h 11e: --00 00h (p+15)h 11f: --00 00h (p+16)h 120: --00 00h (p+17)h 121: --00 0 (p+18)h bits 40?47 = ?n? n = factory pgm'd groups (high byte) 122: --00 0 (p+19)h 123: --00 0 (p+1a)h 124: --10 16 (p+1b)h 125: --00 0 (p+1c)h 126: --04 16 bits 48?55 = ?n? \ 2n = factory programmable bytes/group bits 56?63 = ?n? n = user pgm'd groups (low byte) bits 64?71 = ?n? n = user pg m'd g rou p s ( hi g h b y te ) bits 72?79 = ?n? 2 n = user programmable bytes/group with device-unique serial numbers. others are user programmable. bits 0?15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user-programmable. bits 0?7 = lock/bytes jedec-plane physical low address bits 8?15 = lock/bytes jedec-plane physical high address bits 16?23 = ?n? such that 2 n = factory pre-programmed bytes bits 24?31 = ?n? such that 2 n = user programmable bytes bits 0?31 point to the protection register physical lock-word address in the jedec-plane. following bytes are factory or user-programmable. bits 32?39 = ?n? n = factory pgm'd groups (low byte) number of protection register fields in jedec id space. ?00h,? indicates that 256 protection fields are available offset (1) length descri p tion hex p = 10ah (optional flash features and commands) add. code v alue (p+1d)h 1 127: --03 8 byte (p+1e)h 1 128: --04 4 (p+1f)h 1 129: --01 4 (p+20)h 1 synchronous mode read capability configuration 2 12a: --02 8 (p+21)h 1 synchronous mode read capability configuration 3 12b: --03 16 (p+22)h 1 synchronous mode read capability configuration 4 12c: --07 cont page mode read capability bits 0?7 = ?n? such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read p a g e buffer. number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. synchronous mode read capability configuration 1 bits 3?7 = reserved bits 0?2 ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bits 0?2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data out p ut width.
28f640l30, 28f128l30, 28f256l30 datasheet 89 table 27. partition and erase-block region information offset (1) see table below p= 10ah descri p tion address botto m to p ( o p tional flash features and commands ) len bot top (p+23)h (p+23)h 1 12d: 12d: number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions.
28f640l30, 28f128l30, 28f256l30 90 datasheet partition region 1 information offset (1) see table below p = 10ah descri p tion a ddress bottom to p ( o p tional flash features and commands ) len bot top (p+24)h (p+24)h number of identical partitions within the partition region 2 12e: 12e: (p+25)h (p+25)h 12f: 12f: (p+26)h (p+26)h 1 130: 130: (p+27)h (p+27)h 1 131: 131: (p+28)h (p+28)h 1 132: 132: (p+29)h (p+29)h 1 133: 133: (p+2a)h (p+2a)h partition region 1 erase block type 1 information 4 134: 134: (p+2b)h (p+2b)h bits 0?15 = y, y+1 = number of identical-size erase blocks 135: 135: (p+2c)h (p+2c)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 136: 136: (p+2d)h (p+2d)h 137: 137: (p+2e)h (p+2e)h partition 1 (erase block type 1) 2138:138: (p+2f)h (p+2f)h minimum block erase cycles x 1000 139: 139: (p+30)h (p+30)h 1 13a: 13a: (p+31)h (p+31)h 1 13b: 13b: (p+32)h partition region 1 erase block type 2 information 4 13c: (p+33)h bits 0?15 = y, y+1 = number of identical-size erase blocks 13d: (p+34)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 13e: (p+35)h (bottom parameter device only) 13f: (p+36)h partition 1 (erase block type 2) 2 140: (p+37)h minimum block erase cycles x 1000 141: (p+38)h 1142: (p+39)h 1143: partition 1 (erase block type 1) bits per cell; internal ecc bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 1 (erase block type 1) page mode and synchronous mode capabilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use partition 1 (erase block type 2) bits per cell bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 1 (erase block type 2) pagemode and synchronous mode capabilities defined in table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use number of program or erase operations allowed in a partition bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) +?+ (type n blocks)x(type n block sizes)
28f640l30, 28f128l30, 28f256l30 datasheet 91 partition region 2 information offset (1) see table below p = 10ah descri p tion address bottom to p ( o p tional flash features and commands ) len bot top (p+3a)h (p+32)h number of identical partitions within the partition region 2 144: 13c: (p+3b)h (p+33)h 145: 13d: (p+3c)h (p+34)h 1 146: 13e: (p+3d)h (p+35)h 1 147: 13f: (p+3e)h (p+36)h 1 148: 140: (p+3f)h (p+37)h 1 149: 141: (p+40)h (p+38)h partition region 2 erase block type 1 information 4 14a: 142: (p+41)h (p+39)h bits 0?15 = y, y+1 = number of identical-size erase blocks 14b: 143: (p+42)h (p+3a)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 14c: 144: (p+43)h (p+3b)h 14d: 145: (p+44)h (p+3c)h partition 2 ( erase block t yp e 1 ) 2 14e: 146: (p+45)h (p+3d)h minimum block erase cycles x 1000 14f: 147: (p+46)h (p+3e)h 1 150: 148: (p+47)h (p+3f)h 1 151: 149: (p+40)h partition region 2 erase block type 2 information 4 14a: (p+41)h bits 0?15 = y, y+1 = number of identical-size erase blocks 14b: (p+42)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 14c: (p+43)h 14d: (p+44)h partition 2 ( erase block t yp e 2 ) 214e: (p+45)h minimum block erase cycles x 1000 14f: (p+46)h 1 150: (p+47)h 1 151: partition 2 (erase block type 1) bits per cell bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 2 (erase block type 1) pagemode and synchronous mode capabilities as defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use partition 2 (erase block type 2) bits per cell bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 2 (erase block type 2) pagemode and synchronous mode capabilities as defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use number of program or erase operations allowed in a partition bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) +?+ (type n blocks)x(type n block sizes)
28f640l30, 28f128l30, 28f256l30 92 datasheet partition and erase-block region information address 64 mbit ?b ?t ?b ?t ?b ?t 12d: --02 --02 --02 --02 --02 --02 12e: --01 --07 --01 --0f --01 --0f 12f: --00 --00 --00 --00 --00 --00 130: --11 --11 --11 --11 --11 --11 131: --00 --00 --00 --00 --00 --00 132: --00 --00 --00 --00 --00 --00 133: --02 --01 --02 --01 --02 --01 134: --03 --07 --03 --07 --03 --0f 135: --00 --00 --00 --00 --00 --00 136: --80 --00 --80 --00 --80 --00 137: --00 --02 --00 --02 --00 --02 138: --64 --64 --64 --64 --64 --64 139: --00 --00 --00 --00 --00 --00 13a: --02 --02 --02 --02 --02 --02 13b: --03 --03 --03 --03 --03 --03 13c:--06--01--06--01--0e--01 13d: --00 --00 --00 --00 --00 --00 13e: --00 --11 --00 --11 --00 --11 13f: --02 --00 --02 --00 --02 --00 140: --64 --00 --64 --00 --64 --00 141: --00 --02 --00 --02 --00 --02 142: --02 --06 --02 --06 --02 --0e 143: --03 --00 --03 --00 --03 --00 144: --07 --00 --0f --00 --0f --00 145: --00 --02 --00 --02 --00 --02 146: --11 --64 --11 --64 --11 --64 147: --00 --00 --00 --00 --00 --00 148: --00 --02 --00 --02 --00 --02 149: --01 --03 --01 --03 --01 --03 14a: --07 --03 --07 --03 --0f --03 14b: --00 --00 --00 --00 --00 --00 14c: --00 --80 --00 --80 --00 --80 14d: --02 --00 --02 --00 --02 --00 14e: --64 --64 --64 --64 --64 --64 14f: --00 --00 --00 --00 --00 --00 150: --02 --02 --02 --02 --02 --02 151: --03 --03 --03 --03 --03 --03 128 mbit 256 mbit
28f640l30, 28f128l30, 28f256l30 datasheet 93 appendix d mechanical information figure 39. mechanical specification for the 64- and 128-mbit; 56-ball vf bga package drawing and dimensions e seating plane top view - ball side down bottom view - ball side up y a a1 d a2 a1 index mark s1 s2 e b a1 index mark a b c d e f g 8 7 6 5 4 3 2 1 876 543 21 a b c d e f g note: drawing not to scale side view millimeters inches dimensions symbol min nom max notes min nom max package height a 1.000 0.0394 ball height a1 0.150 0.0059 package body thickness a2 0.665 0.0262 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length (64mb, 128mb) d 7.600 7.700 7.800 0.2992 0.3031 0.3071 package body width 64mb e 6.100 6.200 6.300 0.2402 0.2441 0.2480 package body width 128mb e 8.900 9.000 9.100 0.3504 0.3543 0.3583 pitch e 0.750 0.0295 ball (lead) count n 56 56 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d (64mb, 128mb) s1 1.125 1.225 1.325 0.0443 0.0482 0.0522 corner to ball a1 distance along e 64mb s2 0.750 0.850 0.950 0.0331 0.0335 0.0339 corner to ball a1 distance along e 128mb s2 2.150 2.250 2.350 0.0846 0.0886 0.0925
28f640l30, 28f128l30, 28f256l30 94 datasheet figure 40. mechanical specification for the 256-mbit; 79-ball vf bga package drawing and dimensions dimensions table side view top view - ball side down bottom view - ball side up a2 a seating plane y a1 s2 a1 index mark e b a1 index mark s1 e d a b c d e f g 4 5 6 7321 8 9 10 11 12 13 a b c d e f g 4567 3 2 189 10 11 1213 drawing not to scale millimeters inches dimens ions s ymbol min nom max notes min nom max package height a 1.000 0.0394 ball height a1 0.150 0.0059 package body thicknes s a2 0.665 0.0262 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body len g t h (256mb) d 10.900 11.000 11.100 0.4291 0.4331 0.4370 package body width (256mb) e 8.900 9.000 9.100 0.3504 0.3543 0.3583 pitch e 0.750 0.0295 ball (lead) count n7979 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d s1 0.900 1.000 1.100 0.0354 0.0394 0.0433 corner to ball a1 distance along e s2 2.150 2.250 2.350 0.0846 0.0886 0.0925
28f640l30, 28f128l30, 28f256l30 datasheet 95 figure 41. mechanical specification for the 128-mbit device in an 88-ball (80-active ball) intel ? stacked chip scale package drawing and dimensions millimeters inches di me n s i o n s s y mbo l mi n n o m ma x no t e s mi n n o m ma x package heigh t a 1.200 0.0472 ba l l heigh t a1 0.200 0.0079 package body thickne s s a2 0.860 0.0339 ba l l (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body len g th d 9.900 10.000 10.100 0.3898 0.3937 0.3976 package body width e 7.900 8.000 8.100 0.3110 0.3150 0.3189 pitch e0.800 0.0315 ba l l (lead) count n8888 se atin g plane coplanarity y 0.100 0.0039 co r ne r to ball a1 distance along e s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 co r ne r to ball a1 distance along d s2 0.500 0.600 0.700 0.0197 0.0236 0.0276 top view - ball down bot tom view - ball up a a2 d e y a1 draw ing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mar k 12 345 678 8x10x1.2q
28f640l30, 28f128l30, 28f256l30 96 datasheet figure 42. mechanical specification for the 256-mbit device in an 88-ball (80-active ball) intel ? ultra-thin stacked chip scale package drawing and dimensions millimeters inches dimens ions symbol min nom max notes min nom max package heig ht a 1.00 0.0394 ball height a1 0.117 0.0046 package body thicknes s a2 0.740 0.0291 ball (lead) width b 0.300 0.350 0.400 0.0118 0.0138 0.0157 package body length d 10.900 11.00 11.100 0.4291 0.4331 0.4370 package body width e 7.900 8.00 8.100 0.3110 0.3150 0.3189 pitch e 0.80 0.0315 ball (lead) count n 88 88 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along e s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a1 distance along d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 top view - ball down bot tom view - ball up a a2 d e y a1 drawing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 123 456 78 ut 8x11x1.0q note: dimensions a1, a2, and b are preliminary
28f640l30, 28f128l30, 28f256l30 datasheet 97 appendix e additional information order/document number document/tool 251903 1.8 volt intel strataflash ? wireless memory datasheet with 3-volt i/o 290701 1.8 volt intel ? wireless flash memory datasheet 290702 1.8 volt intel ? wireless flash memory with 3 volt i/o datasheet 290737 3 volt synchronous intel strataflash ? memory datasheet 251908 migration guide for 1.8 volt intel ? wireless flash memory (w18/w30) to 1.8 volt intel strataflash ? wireless memory (l18/l30), application note 753 251909 migration guide for 3 volt synchronous intel strataflash ? memory (k3/k18) to 1.8 volt intel strataflash ? wireless memory (l18/l30), application note 754 298161 intel ? flash memory chip scale package user?s guide 297833 intel ? flash data integrator (fdi) user?s guide 298136 intel ? persistent storage manager user guide notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intel?s world wide web home page at http://www.intel.com for technical documentation and tools. 3. for the most current information on intel strataflash ? memory, visit our website at http:// developer.intel.com/design/flash/isf.
28f640l30, 28f128l30, 28f256l30 98 datasheet appendix f ordering information for vf bga package f 6 4 3 0 t 8 8 e 2 g 0 l 5 product line designator for all intel ? flash products package designator extended temperature (-25 c to +85 c) ge = 0.75mm vf bga t = top parameter blocking b = bottom parameter blocking device density 640 =x 16 (64-mbit) 128 =x 16 (128-mbit) 256 =x 16 (256-mbit) product family l30 = 1.8 volt intel strataflash ? wireless memory with 3.0-volt i/o v cc = 1.7 v - 2.0 v v ccq = 2.2 v - 3.3 v access speed (ns) 85, 110
28f640l30, 28f128l30, 28f256l30 datasheet 99 appendix g ordering information for s-csp package figure 43 shows the decoder for the 1.8 vo l t intel strataflash ? wireless memory in quad+ ballout products. figure 43. decoder for 1.8 volt intel strataflash ? wireless memory (l30) in quad+ ballout table 28. valid combinations for s-csp package i/o 128-mbit 256-mbit 3.0 v i/o rd48f3000l0ztq0 nz48f4000l0ztq0 rd48f3000l0zbq0 nz48f4000l0zbq0 b = bottom pa r a me t e r t = top pa r a me t e r f 3 0 l 0 y b q 8 d 4 r package pinout indicator flash density voltage product family rd = in t el ? stacked ch ip scale package nz = intel? ultr a- thin stacked chip scalepackage 0 = no die 3 = 128-mbit 4 = 256-mbit l = 1.8 volt intel strataflas h ? wireless flash memor y 0 = no die y = 1.8 volt cor e and i/o z = 3 volt i/ o, 1.8 volt cor e q= quad+ ballout 0 0 0 parameter location device details 0 = original version of the products (ref er to the latest version of the datasheet for details). flas h #1 flas h #3 flas h #4 flas h #2 flash family 1/2 flash family 3/4 product line designator 48f = flas h memo r y only
28f640l30, 28f128l30, 28f256l30 100 datasheet

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